Lines Matching +full:cpm +full:- +full:muram
1 // SPDX-License-Identifier: GPL-2.0-or-later
9 /dts-v1/;
16 #address-cells = <1>;
17 #size-cells = <1>;
29 #address-cells = <1>;
30 #size-cells = <0>;
35 d-cache-line-size = <32>;
36 i-cache-line-size = <32>;
37 d-cache-size = <32768>;
38 i-cache-size = <32768>;
39 timebase-frequency = <0>;
40 bus-frequency = <0>;
41 clock-frequency = <0>;
42 next-level-cache = <&L2>;
52 #address-cells = <1>;
53 #size-cells = <1>;
56 bus-frequency = <0>;
57 compatible = "fsl,mpc8560-immr", "simple-bus";
59 ecm-law@0 {
60 compatible = "fsl,ecm-law";
62 fsl,num-laws = <8>;
66 compatible = "fsl,mpc8560-ecm", "fsl,ecm";
69 interrupt-parent = <&mpic>;
72 memory-controller@2000 {
73 compatible = "fsl,mpc8540-memory-controller";
75 interrupt-parent = <&mpic>;
79 L2: l2-cache-controller@20000 {
80 compatible = "fsl,mpc8540-l2-cache-controller";
82 cache-line-size = <32>;
83 cache-size = <0x40000>; // L2, 256K
84 interrupt-parent = <&mpic>;
89 #address-cells = <1>;
90 #size-cells = <0>;
91 cell-index = <0>;
92 compatible = "fsl-i2c";
95 interrupt-parent = <&mpic>;
110 #address-cells = <1>;
111 #size-cells = <1>;
112 compatible = "fsl,mpc8560-dma", "fsl,eloplus-dma";
115 cell-index = <0>;
116 dma-channel@0 {
117 compatible = "fsl,mpc8560-dma-channel",
118 "fsl,eloplus-dma-channel";
120 cell-index = <0>;
121 interrupt-parent = <&mpic>;
124 dma-channel@80 {
125 compatible = "fsl,mpc8560-dma-channel",
126 "fsl,eloplus-dma-channel";
128 cell-index = <1>;
129 interrupt-parent = <&mpic>;
132 dma-channel@100 {
133 compatible = "fsl,mpc8560-dma-channel",
134 "fsl,eloplus-dma-channel";
136 cell-index = <2>;
137 interrupt-parent = <&mpic>;
140 dma-channel@180 {
141 compatible = "fsl,mpc8560-dma-channel",
142 "fsl,eloplus-dma-channel";
144 cell-index = <3>;
145 interrupt-parent = <&mpic>;
151 #address-cells = <1>;
152 #size-cells = <1>;
153 cell-index = <0>;
159 local-mac-address = [ 00 00 00 00 00 00 ];
161 interrupt-parent = <&mpic>;
162 tbi-handle = <&tbi0>;
163 phy-handle = <&phy2>;
166 #address-cells = <1>;
167 #size-cells = <0>;
168 compatible = "fsl,gianfar-mdio";
171 phy1: ethernet-phy@1 {
172 interrupt-parent = <&mpic>;
176 phy2: ethernet-phy@2 {
177 interrupt-parent = <&mpic>;
181 phy3: ethernet-phy@3 {
182 interrupt-parent = <&mpic>;
186 tbi0: tbi-phy@11 {
188 device_type = "tbi-phy";
194 #address-cells = <1>;
195 #size-cells = <1>;
196 cell-index = <1>;
202 local-mac-address = [ 00 00 00 00 00 00 ];
204 interrupt-parent = <&mpic>;
205 tbi-handle = <&tbi1>;
206 phy-handle = <&phy1>;
209 #address-cells = <1>;
210 #size-cells = <0>;
211 compatible = "fsl,gianfar-tbi";
214 tbi1: tbi-phy@11 {
216 device_type = "tbi-phy";
222 interrupt-controller;
223 #address-cells = <0>;
224 #interrupt-cells = <2>;
226 device_type = "open-pic";
227 compatible = "chrp,open-pic";
230 cpm@919c0 {
231 #address-cells = <1>;
232 #size-cells = <1>;
233 compatible = "fsl,mpc8560-cpm", "fsl,cpm2", "simple-bus";
237 muram@80000 {
238 #address-cells = <1>;
239 #size-cells = <1>;
243 compatible = "fsl,cpm-muram-data";
249 compatible = "fsl,mpc8560-brg",
250 "fsl,cpm2-brg",
251 "fsl,cpm-brg";
253 clock-frequency = <0>;
257 interrupt-controller;
258 #address-cells = <0>;
259 #interrupt-cells = <2>;
261 interrupt-parent = <&mpic>;
263 compatible = "fsl,mpc8560-cpm-pic", "fsl,cpm2-pic";
268 compatible = "fsl,mpc8560-scc-uart",
269 "fsl,cpm2-scc-uart";
271 fsl,cpm-brg = <1>;
272 fsl,cpm-command = <0x800000>;
273 current-speed = <115200>;
275 interrupt-parent = <&cpmpic>;
280 compatible = "fsl,mpc8560-scc-uart",
281 "fsl,cpm2-scc-uart";
283 fsl,cpm-brg = <2>;
284 fsl,cpm-command = <0x4a00000>;
285 current-speed = <115200>;
287 interrupt-parent = <&cpmpic>;
292 compatible = "fsl,mpc8560-fcc-enet",
293 "fsl,cpm2-fcc-enet";
295 local-mac-address = [ 00 00 00 00 00 00 ];
296 fsl,cpm-command = <0x1a400300>;
298 interrupt-parent = <&cpmpic>;
299 phy-handle = <&phy3>;
305 compatible = "fsl,mpc8560-localbus", "fsl,pq3-localbus",
306 "simple-bus";
307 #address-cells = <2>;
308 #size-cells = <1>;
310 interrupt-parent = <&mpic>;
320 #address-cells = <1>;
321 #size-cells = <1>;
322 compatible = "cfi-flash";
324 bank-width = <4>;
325 device-width = <1>;
348 label = "u-boot";
350 read-only;
354 /* Note: CAN support needs be enabled in U-Boot */
359 interrupt-parent = <&mpic>;
366 interrupt-parent = <&mpic>;
371 #interrupt-cells = <1>;
372 #size-cells = <2>;
373 #address-cells = <3>;
374 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
377 clock-frequency = <66666666>;
378 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
379 interrupt-map = <
391 interrupt-parent = <&mpic>;
393 bus-range = <0 0>;