Lines Matching +full:cpm +full:- +full:muram
1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /dts-v1/;
15 #address-cells = <1>;
16 #size-cells = <1>;
27 #address-cells = <1>;
28 #size-cells = <0>;
33 d-cache-line-size = <32>;
34 i-cache-line-size = <32>;
35 d-cache-size = <32768>;
36 i-cache-size = <32768>;
37 timebase-frequency = <0>;
38 bus-frequency = <0>;
39 clock-frequency = <0>;
40 next-level-cache = <&L2>;
50 #address-cells = <1>;
51 #size-cells = <1>;
54 bus-frequency = <0>;
55 compatible = "fsl,mpc8555-immr", "simple-bus";
57 ecm-law@0 {
58 compatible = "fsl,ecm-law";
60 fsl,num-laws = <8>;
64 compatible = "fsl,mpc8555-ecm", "fsl,ecm";
67 interrupt-parent = <&mpic>;
70 memory-controller@2000 {
71 compatible = "fsl,mpc8540-memory-controller";
73 interrupt-parent = <&mpic>;
77 L2: l2-cache-controller@20000 {
78 compatible = "fsl,mpc8540-l2-cache-controller";
80 cache-line-size = <32>;
81 cache-size = <0x40000>; // L2, 256K
82 interrupt-parent = <&mpic>;
87 #address-cells = <1>;
88 #size-cells = <0>;
89 cell-index = <0>;
90 compatible = "fsl-i2c";
93 interrupt-parent = <&mpic>;
108 #address-cells = <1>;
109 #size-cells = <1>;
110 compatible = "fsl,mpc8555-dma", "fsl,eloplus-dma";
113 cell-index = <0>;
114 dma-channel@0 {
115 compatible = "fsl,mpc8555-dma-channel",
116 "fsl,eloplus-dma-channel";
118 cell-index = <0>;
119 interrupt-parent = <&mpic>;
122 dma-channel@80 {
123 compatible = "fsl,mpc8555-dma-channel",
124 "fsl,eloplus-dma-channel";
126 cell-index = <1>;
127 interrupt-parent = <&mpic>;
130 dma-channel@100 {
131 compatible = "fsl,mpc8555-dma-channel",
132 "fsl,eloplus-dma-channel";
134 cell-index = <2>;
135 interrupt-parent = <&mpic>;
138 dma-channel@180 {
139 compatible = "fsl,mpc8555-dma-channel",
140 "fsl,eloplus-dma-channel";
142 cell-index = <3>;
143 interrupt-parent = <&mpic>;
149 #address-cells = <1>;
150 #size-cells = <1>;
151 cell-index = <0>;
157 local-mac-address = [ 00 00 00 00 00 00 ];
159 interrupt-parent = <&mpic>;
160 tbi-handle = <&tbi0>;
161 phy-handle = <&phy2>;
164 #address-cells = <1>;
165 #size-cells = <0>;
166 compatible = "fsl,gianfar-mdio";
169 phy1: ethernet-phy@1 {
170 interrupt-parent = <&mpic>;
174 phy2: ethernet-phy@2 {
175 interrupt-parent = <&mpic>;
179 phy3: ethernet-phy@3 {
180 interrupt-parent = <&mpic>;
184 tbi0: tbi-phy@11 {
186 device_type = "tbi-phy";
192 #address-cells = <1>;
193 #size-cells = <1>;
194 cell-index = <1>;
200 local-mac-address = [ 00 00 00 00 00 00 ];
202 interrupt-parent = <&mpic>;
203 tbi-handle = <&tbi1>;
204 phy-handle = <&phy1>;
207 #address-cells = <1>;
208 #size-cells = <0>;
209 compatible = "fsl,gianfar-tbi";
212 tbi1: tbi-phy@11 {
214 device_type = "tbi-phy";
220 cell-index = <0>;
224 clock-frequency = <0>; // should we fill in in uboot?
226 interrupt-parent = <&mpic>;
230 cell-index = <1>;
234 clock-frequency = <0>; // should we fill in in uboot?
236 interrupt-parent = <&mpic>;
243 interrupt-parent = <&mpic>;
244 fsl,num-channels = <4>;
245 fsl,channel-fifo-len = <24>;
246 fsl,exec-units-mask = <0x7e>;
247 fsl,descriptor-types-mask = <0x01010ebf>;
251 interrupt-controller;
252 #address-cells = <0>;
253 #interrupt-cells = <2>;
255 device_type = "open-pic";
256 compatible = "chrp,open-pic";
259 cpm@919c0 {
260 #address-cells = <1>;
261 #size-cells = <1>;
262 compatible = "fsl,mpc8555-cpm", "fsl,cpm2", "simple-bus";
266 muram@80000 {
267 #address-cells = <1>;
268 #size-cells = <1>;
272 compatible = "fsl,cpm-muram-data";
278 compatible = "fsl,mpc8555-brg",
279 "fsl,cpm2-brg",
280 "fsl,cpm-brg";
282 clock-frequency = <0>;
286 interrupt-controller;
287 #address-cells = <0>;
288 #interrupt-cells = <2>;
290 interrupt-parent = <&mpic>;
292 compatible = "fsl,mpc8555-cpm-pic", "fsl,cpm2-pic";
298 #interrupt-cells = <1>;
299 #size-cells = <2>;
300 #address-cells = <3>;
301 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
304 clock-frequency = <66666666>;
305 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
306 interrupt-map = <
318 interrupt-parent = <&mpic>;
320 bus-range = <0 0>;