Lines Matching +full:reg +full:- +full:size
1 // SPDX-License-Identifier: GPL-2.0-or-later
9 /dts-v1/;
14 #address-cells = <1>;
15 #size-cells = <1>;
30 #address-cells = <1>;
31 #size-cells = <0>;
35 reg = <0>;
36 d-cache-line-size = <32>; // 32 bytes
37 i-cache-line-size = <32>; // 32 bytes
38 d-cache-size = <0x8000>; // L1, 32K
39 i-cache-size = <0x8000>; // L1, 32K
40 next-level-cache = <&L2>;
46 reg = <0x00000000 0x00000000>; // Filled in by U-Boot
50 #address-cells = <1>;
51 #size-cells = <1>;
54 bus-frequency = <0>;
55 compatible = "fsl,mpc8548-immr", "simple-bus";
57 ecm-law@0 {
58 compatible = "fsl,ecm-law";
59 reg = <0x0 0x1000>;
60 fsl,num-laws = <10>;
64 compatible = "fsl,mpc8548-ecm", "fsl,ecm";
65 reg = <0x1000 0x1000>;
67 interrupt-parent = <&mpic>;
70 memory-controller@2000 {
71 compatible = "fsl,mpc8548-memory-controller";
72 reg = <0x2000 0x1000>;
73 interrupt-parent = <&mpic>;
77 L2: l2-cache-controller@20000 {
78 compatible = "fsl,mpc8548-l2-cache-controller";
79 reg = <0x20000 0x1000>;
80 cache-line-size = <32>; // 32 bytes
81 cache-size = <0x80000>; // L2, 512K
82 interrupt-parent = <&mpic>;
87 #address-cells = <1>;
88 #size-cells = <0>;
89 cell-index = <0>;
90 compatible = "fsl-i2c";
91 reg = <0x3000 0x100>;
93 interrupt-parent = <&mpic>;
98 reg = <0x48>;
103 reg = <0x68>;
108 #address-cells = <1>;
109 #size-cells = <0>;
110 cell-index = <1>;
111 compatible = "fsl-i2c";
112 reg = <0x3100 0x100>;
114 interrupt-parent = <&mpic>;
119 #address-cells = <1>;
120 #size-cells = <1>;
121 compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma";
122 reg = <0x21300 0x4>;
124 cell-index = <0>;
125 dma-channel@0 {
126 compatible = "fsl,mpc8548-dma-channel",
127 "fsl,eloplus-dma-channel";
128 reg = <0x0 0x80>;
129 cell-index = <0>;
130 interrupt-parent = <&mpic>;
133 dma-channel@80 {
134 compatible = "fsl,mpc8548-dma-channel",
135 "fsl,eloplus-dma-channel";
136 reg = <0x80 0x80>;
137 cell-index = <1>;
138 interrupt-parent = <&mpic>;
141 dma-channel@100 {
142 compatible = "fsl,mpc8548-dma-channel",
143 "fsl,eloplus-dma-channel";
144 reg = <0x100 0x80>;
145 cell-index = <2>;
146 interrupt-parent = <&mpic>;
149 dma-channel@180 {
150 compatible = "fsl,mpc8548-dma-channel",
151 "fsl,eloplus-dma-channel";
152 reg = <0x180 0x80>;
153 cell-index = <3>;
154 interrupt-parent = <&mpic>;
160 #address-cells = <1>;
161 #size-cells = <1>;
162 cell-index = <0>;
166 reg = <0x24000 0x1000>;
168 local-mac-address = [ 00 00 00 00 00 00 ];
170 interrupt-parent = <&mpic>;
171 tbi-handle = <&tbi0>;
172 phy-handle = <&phy2>;
175 #address-cells = <1>;
176 #size-cells = <0>;
177 compatible = "fsl,gianfar-mdio";
178 reg = <0x520 0x20>;
180 phy1: ethernet-phy@0 {
181 interrupt-parent = <&mpic>;
183 reg = <1>;
185 phy2: ethernet-phy@1 {
186 interrupt-parent = <&mpic>;
188 reg = <2>;
190 phy3: ethernet-phy@3 {
191 interrupt-parent = <&mpic>;
193 reg = <3>;
195 phy4: ethernet-phy@4 {
196 interrupt-parent = <&mpic>;
198 reg = <4>;
200 phy5: ethernet-phy@5 {
201 interrupt-parent = <&mpic>;
203 reg = <5>;
205 tbi0: tbi-phy@11 {
206 reg = <0x11>;
207 device_type = "tbi-phy";
213 #address-cells = <1>;
214 #size-cells = <1>;
215 cell-index = <1>;
219 reg = <0x25000 0x1000>;
221 local-mac-address = [ 00 00 00 00 00 00 ];
223 interrupt-parent = <&mpic>;
224 tbi-handle = <&tbi1>;
225 phy-handle = <&phy1>;
228 #address-cells = <1>;
229 #size-cells = <0>;
230 compatible = "fsl,gianfar-tbi";
231 reg = <0x520 0x20>;
233 tbi1: tbi-phy@11 {
234 reg = <0x11>;
235 device_type = "tbi-phy";
241 #address-cells = <1>;
242 #size-cells = <1>;
243 cell-index = <2>;
247 reg = <0x26000 0x1000>;
249 local-mac-address = [ 00 00 00 00 00 00 ];
251 interrupt-parent = <&mpic>;
252 tbi-handle = <&tbi2>;
253 phy-handle = <&phy4>;
256 #address-cells = <1>;
257 #size-cells = <0>;
258 compatible = "fsl,gianfar-tbi";
259 reg = <0x520 0x20>;
261 tbi2: tbi-phy@11 {
262 reg = <0x11>;
263 device_type = "tbi-phy";
269 #address-cells = <1>;
270 #size-cells = <1>;
271 cell-index = <3>;
275 reg = <0x27000 0x1000>;
277 local-mac-address = [ 00 00 00 00 00 00 ];
279 interrupt-parent = <&mpic>;
280 tbi-handle = <&tbi3>;
281 phy-handle = <&phy5>;
284 #address-cells = <1>;
285 #size-cells = <0>;
286 compatible = "fsl,gianfar-tbi";
287 reg = <0x520 0x20>;
289 tbi3: tbi-phy@11 {
290 reg = <0x11>;
291 device_type = "tbi-phy";
297 cell-index = <0>;
300 reg = <0x4500 0x100>; // reg base, size
301 clock-frequency = <0>; // should we fill in in uboot?
302 current-speed = <115200>;
304 interrupt-parent = <&mpic>;
308 cell-index = <1>;
311 reg = <0x4600 0x100>; // reg base, size
312 clock-frequency = <0>; // should we fill in in uboot?
313 current-speed = <115200>;
315 interrupt-parent = <&mpic>;
318 global-utilities@e0000 { // global utilities reg
319 compatible = "fsl,mpc8548-guts";
320 reg = <0xe0000 0x1000>;
321 fsl,has-rstcr;
325 interrupt-controller;
326 #address-cells = <0>;
327 #interrupt-cells = <2>;
328 reg = <0x40000 0x40000>;
329 compatible = "chrp,open-pic";
330 device_type = "open-pic";
335 compatible = "fsl,mpc8548-localbus", "fsl,pq3-localbus",
336 "simple-bus";
337 #address-cells = <2>;
338 #size-cells = <1>;
339 reg = <0xe0005000 0x100>; // BRx, ORx, etc.
340 interrupt-parent = <&mpic>;
352 #address-cells = <1>;
353 #size-cells = <1>;
354 compatible = "cfi-flash";
355 reg = <1 0x0 0x8000000>;
356 bank-width = <4>;
357 device-width = <1>;
361 reg = <0x00000000 0x00200000>;
365 reg = <0x00200000 0x00300000>;
369 reg = <0x00500000 0x07a00000>;
373 reg = <0x07f00000 0x00040000>;
377 reg = <0x07f40000 0x00040000>;
380 label = "u-boot";
381 reg = <0x07f80000 0x00080000>;
382 read-only;
386 /* Note: CAN support needs be enabled in U-Boot */
389 reg = <2 0x0 0x100>;
391 interrupt-parent = <&mpic>;
392 bosch,external-clock-frequency = <16000000>;
393 bosch,disconnect-rx1-input;
394 bosch,disconnect-tx1-output;
395 bosch,iso-low-speed-mux;
396 bosch,clock-out-frequency = <16000000>;
401 reg = <2 0x100 0x100>;
403 interrupt-parent = <&mpic>;
404 bosch,external-clock-frequency = <16000000>;
405 bosch,disconnect-rx1-input;
406 bosch,disconnect-tx1-output;
407 bosch,iso-low-speed-mux;
410 /* Note: NAND support needs to be enabled in U-Boot */
412 #address-cells = <0>;
413 #size-cells = <0>;
414 compatible = "tqc,tqm8548-upm-nand", "fsl,upm-nand";
415 reg = <3 0x0 0x800>;
416 fsl,upm-addr-offset = <0x10>;
417 fsl,upm-cmd-offset = <0x08>;
418 /* Micron MT29F8G08FAB multi-chip device */
419 fsl,upm-addr-line-cs-offsets = <0x0 0x200>;
420 fsl,upm-wait-flags = <0x5>;
421 chip-delay = <25>; // in micro-seconds
424 #address-cells = <1>;
425 #size-cells = <1>;
429 reg = <0x00000000 0x10000000>;
436 #interrupt-cells = <1>;
437 #size-cells = <2>;
438 #address-cells = <3>;
439 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
441 reg = <0xe0008000 0x1000>;
442 clock-frequency = <33333333>;
443 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
444 interrupt-map = <
456 interrupt-parent = <&mpic>;
458 bus-range = <0 0>;
464 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
465 interrupt-map = <
472 interrupt-parent = <&mpic>;
474 bus-range = <0 0xff>;
477 clock-frequency = <33333333>;
478 #interrupt-cells = <1>;
479 #size-cells = <2>;
480 #address-cells = <3>;
481 reg = <0xe000a000 0x1000>;
482 compatible = "fsl,mpc8548-pcie";
485 reg = <0 0 0 0 0>;
486 #size-cells = <2>;
487 #address-cells = <3>;