Lines Matching +full:reg +full:- +full:size
1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /dts-v1/;
15 #address-cells = <1>;
16 #size-cells = <1>;
28 #address-cells = <1>;
29 #size-cells = <0>;
33 reg = <0>;
34 d-cache-line-size = <32>;
35 i-cache-line-size = <32>;
36 d-cache-size = <32768>;
37 i-cache-size = <32768>;
38 timebase-frequency = <0>;
39 bus-frequency = <0>;
40 clock-frequency = <0>;
41 next-level-cache = <&L2>;
47 reg = <0x00000000 0x10000000>;
51 #address-cells = <1>;
52 #size-cells = <1>;
55 bus-frequency = <0>;
56 compatible = "fsl,mpc8540-immr", "simple-bus";
58 ecm-law@0 {
59 compatible = "fsl,ecm-law";
60 reg = <0x0 0x1000>;
61 fsl,num-laws = <8>;
65 compatible = "fsl,mpc8540-ecm", "fsl,ecm";
66 reg = <0x1000 0x1000>;
68 interrupt-parent = <&mpic>;
71 memory-controller@2000 {
72 compatible = "fsl,mpc8540-memory-controller";
73 reg = <0x2000 0x1000>;
74 interrupt-parent = <&mpic>;
78 L2: l2-cache-controller@20000 {
79 compatible = "fsl,mpc8540-l2-cache-controller";
80 reg = <0x20000 0x1000>;
81 cache-line-size = <32>;
82 cache-size = <0x40000>; // L2, 256K
83 interrupt-parent = <&mpic>;
88 #address-cells = <1>;
89 #size-cells = <0>;
90 cell-index = <0>;
91 compatible = "fsl-i2c";
92 reg = <0x3000 0x100>;
94 interrupt-parent = <&mpic>;
99 reg = <0x48>;
104 reg = <0x68>;
109 #address-cells = <1>;
110 #size-cells = <1>;
111 compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma";
112 reg = <0x21300 0x4>;
114 cell-index = <0>;
115 dma-channel@0 {
116 compatible = "fsl,mpc8540-dma-channel",
117 "fsl,eloplus-dma-channel";
118 reg = <0x0 0x80>;
119 cell-index = <0>;
120 interrupt-parent = <&mpic>;
123 dma-channel@80 {
124 compatible = "fsl,mpc8540-dma-channel",
125 "fsl,eloplus-dma-channel";
126 reg = <0x80 0x80>;
127 cell-index = <1>;
128 interrupt-parent = <&mpic>;
131 dma-channel@100 {
132 compatible = "fsl,mpc8540-dma-channel",
133 "fsl,eloplus-dma-channel";
134 reg = <0x100 0x80>;
135 cell-index = <2>;
136 interrupt-parent = <&mpic>;
139 dma-channel@180 {
140 compatible = "fsl,mpc8540-dma-channel",
141 "fsl,eloplus-dma-channel";
142 reg = <0x180 0x80>;
143 cell-index = <3>;
144 interrupt-parent = <&mpic>;
150 #address-cells = <1>;
151 #size-cells = <1>;
152 cell-index = <0>;
156 reg = <0x24000 0x1000>;
158 local-mac-address = [ 00 00 00 00 00 00 ];
160 interrupt-parent = <&mpic>;
161 phy-handle = <&phy2>;
164 #address-cells = <1>;
165 #size-cells = <0>;
166 compatible = "fsl,gianfar-mdio";
167 reg = <0x520 0x20>;
169 phy1: ethernet-phy@1 {
170 interrupt-parent = <&mpic>;
172 reg = <1>;
174 phy2: ethernet-phy@2 {
175 interrupt-parent = <&mpic>;
177 reg = <2>;
179 phy3: ethernet-phy@3 {
180 interrupt-parent = <&mpic>;
182 reg = <3>;
184 tbi0: tbi-phy@11 {
185 reg = <0x11>;
186 device_type = "tbi-phy";
192 #address-cells = <1>;
193 #size-cells = <1>;
194 cell-index = <1>;
198 reg = <0x25000 0x1000>;
200 local-mac-address = [ 00 00 00 00 00 00 ];
202 interrupt-parent = <&mpic>;
203 phy-handle = <&phy1>;
206 #address-cells = <1>;
207 #size-cells = <0>;
208 compatible = "fsl,gianfar-tbi";
209 reg = <0x520 0x20>;
211 tbi1: tbi-phy@11 {
212 reg = <0x11>;
213 device_type = "tbi-phy";
219 #address-cells = <1>;
220 #size-cells = <1>;
221 cell-index = <2>;
225 reg = <0x26000 0x1000>;
227 local-mac-address = [ 00 00 00 00 00 00 ];
229 interrupt-parent = <&mpic>;
230 phy-handle = <&phy3>;
233 #address-cells = <1>;
234 #size-cells = <0>;
235 compatible = "fsl,gianfar-tbi";
236 reg = <0x520 0x20>;
238 tbi2: tbi-phy@11 {
239 reg = <0x11>;
240 device_type = "tbi-phy";
246 cell-index = <0>;
249 reg = <0x4500 0x100>; // reg base, size
250 clock-frequency = <0>; // should we fill in in uboot?
252 interrupt-parent = <&mpic>;
256 cell-index = <1>;
259 reg = <0x4600 0x100>; // reg base, size
260 clock-frequency = <0>; // should we fill in in uboot?
262 interrupt-parent = <&mpic>;
266 interrupt-controller;
267 #address-cells = <0>;
268 #interrupt-cells = <2>;
269 reg = <0x40000 0x40000>;
270 device_type = "open-pic";
271 compatible = "chrp,open-pic";
276 #address-cells = <2>;
277 #size-cells = <1>;
278 compatible = "fsl,mpc8540-localbus", "fsl,pq3-localbus",
279 "simple-bus";
280 reg = <0xe0005000 0x1000>;
281 interrupt-parent = <&mpic>;
287 #address-cells = <1>;
288 #size-cells = <1>;
289 compatible = "cfi-flash";
290 reg = <0x0 0x0 0x02000000>;
291 bank-width = <4>;
292 device-width = <2>;
295 reg = <0x00000000 0x00180000>;
299 reg = <0x00180000 0x01dc0000>;
303 reg = <0x01f40000 0x00040000>;
307 reg = <0x01f80000 0x00040000>;
310 label = "u-boot";
311 reg = <0x01fc0000 0x00040000>;
312 read-only;
318 #interrupt-cells = <1>;
319 #size-cells = <2>;
320 #address-cells = <3>;
321 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
323 reg = <0xe0008000 0x1000>;
324 clock-frequency = <66666666>;
325 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
326 interrupt-map = <
338 interrupt-parent = <&mpic>;
340 bus-range = <0 0>;