Lines Matching +full:0 +full:xe0000300
20 dcr-parent = <&{/cpus/cpu@0}>;
31 #size-cells = <0>;
33 cpu@0 {
36 reg = <0x00000000>;
38 timebase-frequency = <0>; // Filled in by zImage
50 reg = <0x00000000 0x00000000 0x00000000>; // Filled in by zImage
58 dcr-reg = <0x200 0x009>;
59 #address-cells = <0>;
60 #size-cells = <0>;
68 cell-index = <0>;
69 dcr-reg = <0x0c0 0x009>;
70 #address-cells = <0>;
71 #size-cells = <0>;
73 interrupts = <0x1 0x4 0x0 0x4>; /* cascade - first non-critical */
82 dcr-reg = <0x0d0 0x009>;
83 #address-cells = <0>;
84 #size-cells = <0>;
86 interrupts = <0x3 0x4 0x2 0x4>; /* cascade */
94 dcr-reg = <0x210 0x009>;
95 #address-cells = <0>;
96 #size-cells = <0>;
98 interrupts = <0x5 0x4 0x4 0x4>; /* cascade */
105 dcr-reg = <0x0b0 0x003 0x0e0 0x010>;
111 dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */
112 0x030 0x008>; /* L2 cache DCR's */
116 interrupts = <0x17 0x1>;
128 dcr-reg = <0x010 0x002>;
134 dcr-reg = <0x020 0x008 0x00a 0x001>;
140 dcr-reg = <0x100 0x027>;
145 dcr-reg = <0x180 0x062>;
149 interrupts = <0x0 0x1 0x2 0x3 0x4>;
151 #address-cells = <0>;
152 #size-cells = <0>;
153 interrupt-map = </*TXEOB*/ 0x0 &UIC0 0xa 0x4
154 /*RXEOB*/ 0x1 &UIC0 0xb 0x4
155 /*SERR*/ 0x2 &UIC1 0x0 0x4
156 /*TXDE*/ 0x3 &UIC1 0x1 0x4
157 /*RXDE*/ 0x4 &UIC1 0x2 0x4>;
158 interrupt-map-mask = <0xffffffff>;
167 ranges = <0x00000000 0x00000001 0x00000000 0x80000000
168 0x80000000 0x00000001 0x80000000 0x80000000>;
169 dcr-reg = <0x090 0x00b>;
171 interrupts = <0x7 0x4>;
177 dcr-reg = <0x012 0x002>;
186 interrupts = <0x5 0x4>;
189 nor_flash@0,0 {
193 reg = <0x0 0x0 0x4000000>;
196 partition@0 {
198 reg = <0x0 0x180000>;
202 reg = <0x180000 0x200000>;
206 reg = <0x380000 0x3bc0000>;
210 reg = <0x3f40000 0x80000>;
214 reg = <0x3fc0000 0x40000>;
224 reg = <0x40000200 0x00000008>;
225 virtual-reg = <0xe0000200>;
229 interrupts = <0x0 0x4>;
235 reg = <0x40000300 0x00000008>;
236 virtual-reg = <0xe0000300>;
240 interrupts = <0x1 0x4>;
246 reg = <0x40000400 0x00000014>;
248 interrupts = <0x2 0x4>;
253 reg = <0x40000500 0x00000014>;
255 interrupts = <0x3 0x4>;
261 reg = <0x40000700 0x00000020>;
266 reg = <0x40000780 0x0000000c>;
271 reg = <0x40000790 0x00000008>;
276 reg = <0x40000b50 0x00000030>;
281 reg = <0x40000d50 0x00000030>;
285 unused = <0x1>;
289 interrupts = <0x1c 0x4 0x1d 0x4>;
290 reg = <0x40000800 0x00000074>;
293 mal-tx-channel = <0>;
294 mal-rx-channel = <0>;
295 cell-index = <0>;
300 phy-map = <0x00000001>;
302 zmii-channel = <0>;
305 unused = <0x1>;
309 interrupts = <0x1e 0x4 0x1f 0x4>;
310 reg = <0x40000900 0x00000074>;
320 phy-map = <0x00000001>;
329 interrupts = <0x0 0x4 0x1 0x4>;
330 reg = <0x40000c00 0x00000074>;
342 rgmii-channel = <0>;
346 tah-channel = <0>;
353 interrupts = <0x2 0x4 0x3 0x4>;
354 reg = <0x40000e00 0x00000074>;
370 tah-channel = <0>;
376 reg = <0x40000a00 0x000000d4>;
378 interrupts = <0x12 0x4 0x13 0x4 0x14 0x4 0x15 0x4 0x16 0x4>;
392 reg = <0x00000002 0x0ec00000 0x00000008 /* Config space access */
393 0x00000000 0x00000000 0x00000000 /* no IACK cycles */
394 0x00000002 0x0ed00000 0x00000004 /* Special cycles */
395 0x00000002 0x0ec80000 0x00000100 /* Internal registers */
396 0x00000002 0x0ec80100 0x000000fc>; /* Internal messaging registers */
401 ranges = <0x02000000 0x00000000 0x80000000 0x00000003 0x80000000 0x00000000 0x80000000
402 0x01000000 0x00000000 0x00000000 0x00000002 0x08000000 0x00000000 0x00010000>;
404 /* Inbound 2GB range starting at 0 */
405 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
407 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
410 0x800 0x0 0x0 0x1 &UIC0 0x17 0x8
411 0x800 0x0 0x0 0x2 &UIC0 0x18 0x8
412 0x800 0x0 0x0 0x3 &UIC0 0x19 0x8
413 0x800 0x0 0x0 0x4 &UIC0 0x1a 0x8
416 0x1000 0x0 0x0 0x1 &UIC0 0x18 0x8
417 0x1000 0x0 0x0 0x2 &UIC0 0x19 0x8
418 0x1000 0x0 0x0 0x3 &UIC0 0x1a 0x8
419 0x1000 0x0 0x0 0x4 &UIC0 0x17 0x8