Lines Matching +full:cpm +full:- +full:muram
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * MPC8555-based STx GP3 Device Tree Source
10 /dts-v1/;
16 compatible = "stx,gp3-8560", "stx,gp3";
17 #address-cells = <1>;
18 #size-cells = <1>;
29 #address-cells = <1>;
30 #size-cells = <0>;
35 d-cache-line-size = <32>; // 32 bytes
36 i-cache-line-size = <32>; // 32 bytes
37 d-cache-size = <0x8000>; // L1, 32K
38 i-cache-size = <0x8000>; // L1, 32K
39 timebase-frequency = <0>; // 33 MHz, from uboot
40 bus-frequency = <0>; // 166 MHz
41 clock-frequency = <0>; // 825 MHz, from uboot
42 next-level-cache = <&L2>;
52 #address-cells = <1>;
53 #size-cells = <1>;
55 compatible = "simple-bus";
57 bus-frequency = <0>;
59 ecm-law@0 {
60 compatible = "fsl,ecm-law";
62 fsl,num-laws = <8>;
66 compatible = "fsl,mpc8555-ecm", "fsl,ecm";
69 interrupt-parent = <&mpic>;
72 memory-controller@2000 {
73 compatible = "fsl,mpc8555-memory-controller";
75 interrupt-parent = <&mpic>;
79 L2: l2-cache-controller@20000 {
80 compatible = "fsl,mpc8555-l2-cache-controller";
82 cache-line-size = <32>; // 32 bytes
83 cache-size = <0x40000>; // L2, 256K
84 interrupt-parent = <&mpic>;
89 #address-cells = <1>;
90 #size-cells = <0>;
91 cell-index = <0>;
92 compatible = "fsl-i2c";
95 interrupt-parent = <&mpic>;
100 #address-cells = <1>;
101 #size-cells = <1>;
102 compatible = "fsl,mpc8555-dma", "fsl,eloplus-dma";
105 cell-index = <0>;
106 dma-channel@0 {
107 compatible = "fsl,mpc8555-dma-channel",
108 "fsl,eloplus-dma-channel";
110 cell-index = <0>;
111 interrupt-parent = <&mpic>;
114 dma-channel@80 {
115 compatible = "fsl,mpc8555-dma-channel",
116 "fsl,eloplus-dma-channel";
118 cell-index = <1>;
119 interrupt-parent = <&mpic>;
122 dma-channel@100 {
123 compatible = "fsl,mpc8555-dma-channel",
124 "fsl,eloplus-dma-channel";
126 cell-index = <2>;
127 interrupt-parent = <&mpic>;
130 dma-channel@180 {
131 compatible = "fsl,mpc8555-dma-channel",
132 "fsl,eloplus-dma-channel";
134 cell-index = <3>;
135 interrupt-parent = <&mpic>;
141 #address-cells = <1>;
142 #size-cells = <1>;
143 cell-index = <0>;
149 local-mac-address = [ 00 00 00 00 00 00 ];
151 interrupt-parent = <&mpic>;
152 tbi-handle = <&tbi0>;
153 phy-handle = <&phy0>;
156 #address-cells = <1>;
157 #size-cells = <0>;
158 compatible = "fsl,gianfar-mdio";
161 phy0: ethernet-phy@2 {
162 interrupt-parent = <&mpic>;
166 phy1: ethernet-phy@4 {
167 interrupt-parent = <&mpic>;
171 tbi0: tbi-phy@11 {
173 device_type = "tbi-phy";
179 #address-cells = <1>;
180 #size-cells = <1>;
181 cell-index = <1>;
187 local-mac-address = [ 00 00 00 00 00 00 ];
189 interrupt-parent = <&mpic>;
190 tbi-handle = <&tbi1>;
191 phy-handle = <&phy1>;
194 #address-cells = <1>;
195 #size-cells = <0>;
196 compatible = "fsl,gianfar-tbi";
199 tbi1: tbi-phy@11 {
201 device_type = "tbi-phy";
207 cell-index = <0>;
211 clock-frequency = <0>; // should we fill in in uboot?
213 interrupt-parent = <&mpic>;
217 cell-index = <1>;
221 clock-frequency = <0>; // should we fill in in uboot?
223 interrupt-parent = <&mpic>;
230 interrupt-parent = <&mpic>;
231 fsl,num-channels = <4>;
232 fsl,channel-fifo-len = <24>;
233 fsl,exec-units-mask = <0x7e>;
234 fsl,descriptor-types-mask = <0x01010ebf>;
238 interrupt-controller;
239 #address-cells = <0>;
240 #interrupt-cells = <2>;
242 compatible = "chrp,open-pic";
243 device_type = "open-pic";
246 cpm@919c0 {
247 #address-cells = <1>;
248 #size-cells = <1>;
249 compatible = "fsl,mpc8555-cpm", "fsl,cpm2";
253 muram@80000 {
254 #address-cells = <1>;
255 #size-cells = <1>;
259 compatible = "fsl,cpm-muram-data";
265 compatible = "fsl,mpc8555-brg",
266 "fsl,cpm2-brg",
267 "fsl,cpm-brg";
272 interrupt-controller;
273 #address-cells = <0>;
274 #interrupt-cells = <2>;
276 interrupt-parent = <&mpic>;
278 compatible = "fsl,mpc8555-cpm-pic", "fsl,cpm2-pic";
284 interrupt-map-mask = <0x1f800 0x0 0x0 0x7>;
285 interrupt-map = <
329 interrupt-parent = <&mpic>;
331 bus-range = <0 0>;
334 clock-frequency = <66666666>;
335 #interrupt-cells = <1>;
336 #size-cells = <2>;
337 #address-cells = <3>;
339 compatible = "fsl,mpc8540-pci";
343 interrupt-controller;
344 device_type = "interrupt-controller";
346 #address-cells = <0>;
347 #interrupt-cells = <2>;
350 interrupt-parent = <&pci0>;
355 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
356 interrupt-map = <
363 interrupt-parent = <&mpic>;
365 bus-range = <0 0>;
368 clock-frequency = <66666666>;
369 #interrupt-cells = <1>;
370 #size-cells = <2>;
371 #address-cells = <3>;
373 compatible = "fsl,mpc8540-pci";