Lines Matching +full:0 +full:x24000
30 #size-cells = <0>;
32 PowerPC,8555@0 {
34 reg = <0x0>;
37 d-cache-size = <0x8000>; // L1, 32K
38 i-cache-size = <0x8000>; // L1, 32K
39 timebase-frequency = <0>; // 33 MHz, from uboot
40 bus-frequency = <0>; // 166 MHz
41 clock-frequency = <0>; // 825 MHz, from uboot
48 reg = <0x00000000 0x10000000>;
56 ranges = <0x0 0xe0000000 0x100000>;
57 bus-frequency = <0>;
59 ecm-law@0 {
61 reg = <0x0 0x1000>;
67 reg = <0x1000 0x1000>;
74 reg = <0x2000 0x1000>;
81 reg = <0x20000 0x1000>;
83 cache-size = <0x40000>; // L2, 256K
90 #size-cells = <0>;
91 cell-index = <0>;
93 reg = <0x3000 0x100>;
103 reg = <0x21300 0x4>;
104 ranges = <0x0 0x21100 0x200>;
105 cell-index = <0>;
106 dma-channel@0 {
109 reg = <0x0 0x80>;
110 cell-index = <0>;
117 reg = <0x80 0x80>;
125 reg = <0x100 0x80>;
133 reg = <0x180 0x80>;
143 cell-index = <0>;
147 reg = <0x24000 0x1000>;
148 ranges = <0x0 0x24000 0x1000>;
157 #size-cells = <0>;
159 reg = <0x520 0x20>;
164 reg = <0x2>;
169 reg = <0x4>;
172 reg = <0x11>;
185 reg = <0x25000 0x1000>;
186 ranges = <0x0 0x25000 0x1000>;
195 #size-cells = <0>;
197 reg = <0x520 0x20>;
200 reg = <0x11>;
207 cell-index = <0>;
210 reg = <0x4500 0x100>; // reg base, size
211 clock-frequency = <0>; // should we fill in in uboot?
220 reg = <0x4600 0x100>; // reg base, size
221 clock-frequency = <0>; // should we fill in in uboot?
227 compatible = "fsl,sec2.0";
228 reg = <0x30000 0x10000>;
233 fsl,exec-units-mask = <0x7e>;
234 fsl,descriptor-types-mask = <0x01010ebf>;
239 #address-cells = <0>;
241 reg = <0x40000 0x40000>;
250 reg = <0x919c0 0x30>;
256 ranges = <0x0 0x80000 0x10000>;
258 data@0 {
260 reg = <0x0 0x2000 0x9000 0x1000>;
268 reg = <0x919f0 0x10 0x915f0 0x10>;
273 #address-cells = <0>;
277 reg = <0x90c00 0x80>;
284 interrupt-map-mask = <0x1f800 0x0 0x0 0x7>;
287 /* IDSEL 0x10 */
288 0x8000 0x0 0x0 0x1 &mpic 0x0 0x1
289 0x8000 0x0 0x0 0x2 &mpic 0x1 0x1
290 0x8000 0x0 0x0 0x3 &mpic 0x2 0x1
291 0x8000 0x0 0x0 0x4 &mpic 0x3 0x1
293 /* IDSEL 0x11 */
294 0x8800 0x0 0x0 0x1 &mpic 0x0 0x1
295 0x8800 0x0 0x0 0x2 &mpic 0x1 0x1
296 0x8800 0x0 0x0 0x3 &mpic 0x2 0x1
297 0x8800 0x0 0x0 0x4 &mpic 0x3 0x1
299 /* IDSEL 0x12 (Slot 1) */
300 0x9000 0x0 0x0 0x1 &mpic 0x0 0x1
301 0x9000 0x0 0x0 0x2 &mpic 0x1 0x1
302 0x9000 0x0 0x0 0x3 &mpic 0x2 0x1
303 0x9000 0x0 0x0 0x4 &mpic 0x3 0x1
305 /* IDSEL 0x13 (Slot 2) */
306 0x9800 0x0 0x0 0x1 &mpic 0x1 0x1
307 0x9800 0x0 0x0 0x2 &mpic 0x2 0x1
308 0x9800 0x0 0x0 0x3 &mpic 0x3 0x1
309 0x9800 0x0 0x0 0x4 &mpic 0x0 0x1
311 /* IDSEL 0x14 (Slot 3) */
312 0xa000 0x0 0x0 0x1 &mpic 0x2 0x1
313 0xa000 0x0 0x0 0x2 &mpic 0x3 0x1
314 0xa000 0x0 0x0 0x3 &mpic 0x0 0x1
315 0xa000 0x0 0x0 0x4 &mpic 0x1 0x1
317 /* IDSEL 0x15 (Slot 4) */
318 0xa800 0x0 0x0 0x1 &mpic 0x3 0x1
319 0xa800 0x0 0x0 0x2 &mpic 0x0 0x1
320 0xa800 0x0 0x0 0x3 &mpic 0x1 0x1
321 0xa800 0x0 0x0 0x4 &mpic 0x2 0x1
324 /* IDSEL 0x12 (ISA bridge) */
325 0x19000 0x0 0x0 0x1 &mpic 0x0 0x1
326 0x19000 0x0 0x0 0x2 &mpic 0x1 0x1
327 0x19000 0x0 0x0 0x3 &mpic 0x2 0x1
328 0x19000 0x0 0x0 0x4 &mpic 0x3 0x1>;
331 bus-range = <0 0>;
332 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
333 0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>;
338 reg = <0xe0008000 0x1000>;
345 reg = <0x19000 0x0 0x0 0x0 0x1>;
346 #address-cells = <0>;
355 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
358 /* IDSEL 0x15 */
359 0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
360 0xa800 0x0 0x0 0x2 &mpic 0xb 0x1
361 0xa800 0x0 0x0 0x3 &mpic 0xb 0x1
362 0xa800 0x0 0x0 0x4 &mpic 0xb 0x1>;
365 bus-range = <0 0>;
366 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
367 0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>;
372 reg = <0xe0009000 0x1000>;