Lines Matching +full:0 +full:xfa000000
25 #size-cells = <0>;
27 PowerPC,8379@0 {
29 reg = <0x0>;
34 timebase-frequency = <0>;
35 bus-frequency = <0>;
36 clock-frequency = <0>;
42 reg = <0x00000000 0x10000000>; // 256MB at 0
49 reg = <0xe0005000 0x1000>;
50 interrupts = <77 0x8>;
56 ranges = <0x0 0x0 0xfe000000 0x00800000
57 0x1 0x0 0xe0600000 0x00008000
58 0x2 0x0 0xf0000000 0x00020000
59 0x3 0x0 0xfa000000 0x00008000>;
61 flash@0,0 {
65 reg = <0x0 0x0 0x800000>;
70 nand@1,0 {
75 reg = <0x1 0x0 0x8000>;
77 u-boot@0 {
78 reg = <0x0 0x100000>;
83 reg = <0x100000 0x300000>;
86 reg = <0x400000 0x1c00000>;
96 ranges = <0x0 0xe0000000 0x00100000>;
97 reg = <0xe0000000 0x00000200>;
98 bus-frequency = <0>;
103 reg = <0x200 0x100>;
109 reg = <0xc00 0x100>;
110 interrupts = <74 0x8>;
118 reg = <0xd00 0x100>;
119 interrupts = <75 0x8>;
128 sleep = <&pmc 0x0c000000>;
133 #size-cells = <0>;
134 cell-index = <0>;
136 reg = <0x3000 0x100>;
137 interrupts = <14 0x8>;
143 reg = <0x48>;
148 reg = <0x50>;
153 reg = <0x68>;
160 reg = <0x0a>;
167 reg = <0x2e000 0x1000>;
168 interrupts = <42 0x8>;
178 #size-cells = <0>;
181 reg = <0x3100 0x100>;
182 interrupts = <15 0x8>;
188 cell-index = <0>;
190 reg = <0x7000 0x1000>;
191 interrupts = <16 0x8>;
200 reg = <0x82a8 4>;
201 ranges = <0 0x8100 0x1a8>;
204 cell-index = <0>;
205 dma-channel@0 {
207 reg = <0 0x80>;
208 cell-index = <0>;
214 reg = <0x80 0x80>;
221 reg = <0x100 0x80>;
228 reg = <0x180 0x28>;
237 reg = <0x23000 0x1000>;
239 #size-cells = <0>;
241 interrupts = <38 0x8>;
243 sleep = <&pmc 0x00c00000>;
249 cell-index = <0>;
253 reg = <0x24000 0x1000>;
254 ranges = <0x0 0x24000 0x1000>;
256 interrupts = <32 0x8 33 0x8 34 0x8>;
261 sleep = <&pmc 0xc0000000>;
266 #size-cells = <0>;
268 reg = <0x520 0x20>;
272 interrupts = <17 0x8>;
273 reg = <0x2>;
277 reg = <0x11>;
290 reg = <0x25000 0x1000>;
291 ranges = <0x0 0x25000 0x1000>;
293 interrupts = <35 0x8 36 0x8 37 0x8>;
296 fixed-link = <1 1 1000 0 0>;
298 sleep = <&pmc 0x30000000>;
303 #size-cells = <0>;
305 reg = <0x520 0x20>;
308 reg = <0x11>;
315 cell-index = <0>;
318 reg = <0x4500 0x100>;
319 clock-frequency = <0>;
320 interrupts = <9 0x8>;
328 reg = <0x4600 0x100>;
329 clock-frequency = <0>;
330 interrupts = <10 0x8>;
335 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
336 "fsl,sec2.1", "fsl,sec2.0";
337 reg = <0x30000 0x10000>;
338 interrupts = <11 0x8>;
342 fsl,exec-units-mask = <0x9fe>;
343 fsl,descriptor-types-mask = <0x3ab0ebf>;
344 sleep = <&pmc 0x03000000>;
349 reg = <0x18000 0x1000>;
350 interrupts = <44 0x8>;
352 sleep = <&pmc 0x000000c0>;
357 reg = <0x19000 0x1000>;
358 interrupts = <45 0x8>;
360 sleep = <&pmc 0x00000030>;
365 reg = <0x1a000 0x1000>;
366 interrupts = <46 0x8>;
368 sleep = <&pmc 0x0000000c>;
373 reg = <0x1b000 0x1000>;
374 interrupts = <47 0x8>;
376 sleep = <&pmc 0x00000003>;
388 #address-cells = <0>;
390 reg = <0x700 0x100>;
395 reg = <0xb00 0x100 0xa00 0x100>;
396 interrupts = <80 0x8>;
402 interrupt-map-mask = <0xf800 0 0 7>;
404 /* IRQ5 = 21 = 0x15, IRQ6 = 0x16, IRQ7 = 23 = 0x17 */
407 0x7000 0x0 0x0 0x1 &ipic 22 0x8
410 0x7800 0x0 0x0 0x1 &ipic 21 0x8
411 0x7800 0x0 0x0 0x2 &ipic 22 0x8
412 0x7800 0x0 0x0 0x4 &ipic 23 0x8
415 0xE000 0x0 0x0 0x1 &ipic 23 0x8
416 0xE000 0x0 0x0 0x2 &ipic 21 0x8
417 0xE000 0x0 0x0 0x3 &ipic 22 0x8>;
419 interrupts = <66 0x8>;
420 bus-range = <0x0 0x0>;
421 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
422 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
423 0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>;
424 sleep = <&pmc 0x00010000>;
429 reg = <0xe0008500 0x100 /* internal registers */
430 0xe0008300 0x8>; /* config space access registers */
439 gpios = <&mcu_pio 0 0>;
444 gpios = <&mcu_pio 1 0>;