Lines Matching +full:2 +full:- +full:cell
1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright 2007-2008 MontaVista Software, Inc.
11 /dts-v1/;
14 #address-cells = <1>;
15 #size-cells = <1>;
31 #address-cells = <1>;
32 #size-cells = <0>;
37 d-cache-line-size = <32>;
38 i-cache-line-size = <32>;
39 d-cache-size = <32768>;
40 i-cache-size = <32768>;
41 /* filled by u-boot */
42 timebase-frequency = <0>;
43 bus-frequency = <0>;
44 clock-frequency = <0>;
50 /* filled by u-boot */
55 #address-cells = <1>;
56 #size-cells = <1>;
58 compatible = "fsl,mpc8360-immr", "fsl,immr", "fsl,soc",
59 "simple-bus";
62 /* filled by u-boot */
63 bus-frequency = <0>;
71 compatible = "fsl,mpc8360-pmc", "fsl,mpc8349-pmc";
74 interrupt-parent = <&ipic>;
78 #address-cells = <1>;
79 #size-cells = <0>;
80 cell-index = <0>;
81 compatible = "fsl-i2c";
84 interrupt-parent = <&ipic>;
89 #address-cells = <1>;
90 #size-cells = <0>;
91 cell-index = <1>;
92 compatible = "fsl-i2c";
95 interrupt-parent = <&ipic>;
104 interrupt-parent = <&ipic>;
105 /* filled by u-boot */
106 clock-frequency = <0>;
114 interrupt-parent = <&ipic>;
115 /* filled by u-boot */
116 clock-frequency = <0>;
120 #address-cells = <1>;
121 #size-cells = <1>;
122 compatible = "fsl,mpc8360-dma", "fsl,elo-dma";
125 interrupt-parent = <&ipic>;
127 cell-index = <0>;
128 dma-channel@0 {
129 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
131 cell-index = <0>;
132 interrupt-parent = <&ipic>;
135 dma-channel@80 {
136 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
138 cell-index = <1>;
139 interrupt-parent = <&ipic>;
142 dma-channel@100 {
143 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
145 cell-index = <2>;
146 interrupt-parent = <&ipic>;
149 dma-channel@180 {
150 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
152 cell-index = <3>;
153 interrupt-parent = <&ipic>;
162 interrupt-parent = <&ipic>;
163 fsl,num-channels = <4>;
164 fsl,channel-fifo-len = <24>;
165 fsl,exec-units-mask = <0x7e>;
166 fsl,descriptor-types-mask = <0x01010ebf>;
170 ipic: interrupt-controller@700 {
171 #address-cells = <0>;
172 #interrupt-cells = <2>;
173 compatible = "fsl,pq2pro-pic", "fsl,ipic";
174 interrupt-controller;
178 qe_pio_b: gpio-controller@1418 {
179 #gpio-cells = <2>;
180 compatible = "fsl,mpc8360-qe-pario-bank",
181 "fsl,mpc8323-qe-pario-bank";
183 gpio-controller;
186 qe_pio_e: gpio-controller@1460 {
187 #gpio-cells = <2>;
188 compatible = "fsl,mpc8360-qe-pario-bank",
189 "fsl,mpc8323-qe-pario-bank";
191 gpio-controller;
195 #address-cells = <1>;
196 #size-cells = <1>;
198 compatible = "fsl,qe", "simple-bus";
201 /* filled by u-boot */
202 clock-frequency = <0>;
203 bus-frequency = <0>;
204 brg-frequency = <0>;
205 fsl,qe-num-riscs = <2>;
206 fsl,qe-num-snums = <28>;
209 #address-cells = <1>;
210 #size-cells = <1>;
211 compatible = "fsl,qe-muram", "fsl,cpm-muram";
214 data-only@0 {
215 compatible = "fsl,qe-muram-data",
216 "fsl,cpm-muram-data";
222 compatible = "fsl,mpc8360-qe-gtm",
223 "fsl,qe-gtm", "fsl,gtm";
226 interrupt-parent = <&qeic>;
227 clock-frequency = <166666666>;
231 compatible = "fsl,mpc8360-qe-usb",
232 "fsl,mpc8323-qe-usb";
235 interrupt-parent = <&qeic>;
236 fsl,fullspeed-clock = "clk21";
237 gpios = <&qe_pio_b 2 0 /* USBOE */
247 cell-index = <0>;
250 interrupts = <2>;
251 interrupt-parent = <&qeic>;
252 mode = "cpu-qe";
256 cell-index = <1>;
260 interrupt-parent = <&qeic>;
261 mode = "cpu-qe";
267 cell-index = <1>;
270 interrupt-parent = <&qeic>;
271 rx-clock-name = "none";
272 tx-clock-name = "clk9";
273 phy-handle = <&phy2>;
274 phy-connection-type = "rgmii-rxid";
275 /* filled by u-boot */
276 local-mac-address = [ 00 00 00 00 00 00 ];
282 cell-index = <2>;
285 interrupt-parent = <&qeic>;
286 rx-clock-name = "none";
287 tx-clock-name = "clk4";
288 phy-handle = <&phy4>;
289 phy-connection-type = "rgmii-rxid";
290 /* filled by u-boot */
291 local-mac-address = [ 00 00 00 00 00 00 ];
297 cell-index = <7>;
300 interrupt-parent = <&qeic>;
301 rx-clock-name = "clk20";
302 tx-clock-name = "clk19";
303 phy-handle = <&phy1>;
304 phy-connection-type = "mii";
305 /* filled by u-boot */
306 local-mac-address = [ 00 00 00 00 00 00 ];
312 cell-index = <4>;
315 interrupt-parent = <&qeic>;
316 rx-clock-name = "clk8";
317 tx-clock-name = "clk7";
318 phy-handle = <&phy3>;
319 phy-connection-type = "mii";
320 /* filled by u-boot */
321 local-mac-address = [ 00 00 00 00 00 00 ];
325 #address-cells = <1>;
326 #size-cells = <0>;
327 compatible = "fsl,ucc-mdio";
330 phy1: ethernet-phy@1 {
335 phy2: ethernet-phy@2 {
337 reg = <2>;
340 phy3: ethernet-phy@3 {
345 phy4: ethernet-phy@4 {
355 cell-index = <5>;
356 port-number = <0>;
357 rx-clock-name = "brg7";
358 tx-clock-name = "brg8";
360 interrupt-parent = <&qeic>;
361 soft-uart;
368 cell-index = <6>;
369 port-number = <1>;
370 rx-clock-name = "brg13";
371 tx-clock-name = "brg14";
373 interrupt-parent = <&qeic>;
374 soft-uart;
377 qeic: interrupt-controller@80 {
378 #address-cells = <0>;
379 #interrupt-cells = <1>;
380 compatible = "fsl,qe-ic";
381 interrupt-controller;
383 big-endian;
385 interrupt-parent = <&ipic>;
391 #address-cells = <2>;
392 #size-cells = <1>;
393 compatible = "fsl,mpc8360-localbus", "fsl,pq2pro-localbus",
394 "simple-bus";
398 2 0 0x70000000 0x4000000>;
401 compatible = "intel,PC28F640P30T85", "cfi-flash";
403 bank-width = <2>;
404 device-width = <1>;
408 compatible = "fsl,upm-nand";
410 fsl,upm-addr-offset = <16>;
411 fsl,upm-cmd-offset = <8>;
415 compatible = "st,nand512-a";
419 display@2,0 {
422 reg = <2 0 0x4000000>;
424 little-endian;
425 /* filled by u-boot */
431 /* linux,opened; - added by uboot */
436 #address-cells = <3>;
437 #size-cells = <2>;
438 #interrupt-cells = <1>;
440 compatible = "fsl,mpc8360-pci", "fsl,mpc8349-pci";
447 interrupt-parent = <&ipic>;
448 interrupt-map-mask = <0xf800 0 0 7>;
449 interrupt-map = </* miniPCI0 IDSEL 0x14 AD20 */
451 0xa000 0 0 2 &ipic 19 8
455 0xa800 0 0 2 &ipic 20 8
459 /* filled by u-boot */
460 bus-range = <0 0>;
461 clock-frequency = <0>;