Lines Matching +full:0 +full:xe000a000
28 #size-cells = <0>;
30 PowerPC,8315@0 {
32 reg = <0x0>;
37 timebase-frequency = <0>; // from bootloader
38 bus-frequency = <0>; // from bootloader
39 clock-frequency = <0>; // from bootloader
45 reg = <0x00000000 0x08000000>; // 128MB at 0
52 reg = <0xe0005000 0x1000>;
53 interrupts = <77 0x8>;
59 ranges = <0x0 0x0 0xfe000000 0x00800000
60 0x1 0x0 0xe0600000 0x00002000
61 0x2 0x0 0xf0000000 0x00020000
62 0x3 0x0 0xfa000000 0x00008000>;
64 flash@0,0 {
68 reg = <0x0 0x0 0x800000>;
73 nand@1,0 {
78 reg = <0x1 0x0 0x2000>;
80 u-boot@0 {
81 reg = <0x0 0x100000>;
86 reg = <0x100000 0x300000>;
89 reg = <0x400000 0x1c00000>;
99 ranges = <0 0xe0000000 0x00100000>;
100 reg = <0xe0000000 0x00000200>;
101 bus-frequency = <0>;
106 reg = <0x200 0x100>;
111 #size-cells = <0>;
112 cell-index = <0>;
114 reg = <0x3000 0x100>;
115 interrupts = <14 0x8>;
120 reg = <0x68>;
127 reg = <0x0a>;
133 cell-index = <0>;
135 reg = <0x7000 0x1000>;
136 interrupts = <16 0x8>;
145 reg = <0x82a8 4>;
146 ranges = <0 0x8100 0x1a8>;
149 cell-index = <0>;
150 dma-channel@0 {
152 reg = <0 0x80>;
153 cell-index = <0>;
159 reg = <0x80 0x80>;
166 reg = <0x100 0x80>;
173 reg = <0x180 0x28>;
182 reg = <0x23000 0x1000>;
184 #size-cells = <0>;
186 interrupts = <38 0x8>;
193 cell-index = <0>;
197 reg = <0x24000 0x1000>;
198 ranges = <0x0 0x24000 0x1000>;
200 interrupts = <32 0x8 33 0x8 34 0x8>;
208 #size-cells = <0>;
210 reg = <0x520 0x20>;
212 phy0: ethernet-phy@0 {
214 interrupts = <20 0x8>;
215 reg = <0x0>;
220 interrupts = <19 0x8>;
221 reg = <0x1>;
225 reg = <0x11>;
238 reg = <0x25000 0x1000>;
239 ranges = <0x0 0x25000 0x1000>;
241 interrupts = <35 0x8 36 0x8 37 0x8>;
249 #size-cells = <0>;
251 reg = <0x520 0x20>;
254 reg = <0x11>;
261 cell-index = <0>;
264 reg = <0x4500 0x100>;
266 interrupts = <9 0x8>;
274 reg = <0x4600 0x100>;
276 interrupts = <10 0x8>;
281 compatible = "fsl,sec3.3", "fsl,sec3.1", "fsl,sec3.0",
283 "fsl,sec2.0";
284 reg = <0x30000 0x10000>;
285 interrupts = <11 0x8>;
289 fsl,exec-units-mask = <0x97c>;
290 fsl,descriptor-types-mask = <0x3a30abf>;
295 reg = <0x18000 0x1000>;
297 interrupts = <44 0x8>;
303 reg = <0x19000 0x1000>;
305 interrupts = <45 0x8>;
311 reg = <0x500 0x100>;
319 reg = <0x600 0x100>;
333 #address-cells = <0>;
335 reg = <0x700 0x100>;
341 reg = <0x7c0 0x40>;
342 msi-available-ranges = <0 0x100>;
343 interrupts = <0x43 0x8
344 0x4 0x8
345 0x51 0x8
346 0x52 0x8
347 0x56 0x8
348 0x57 0x8
349 0x58 0x8
350 0x59 0x8>;
357 reg = <0xb00 0x100 0xa00 0x100>;
365 reg = <0xc00 0x100>;
374 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
376 /* IDSEL 0x0E -mini PCI */
377 0x7000 0x0 0x0 0x1 &ipic 18 0x8
378 0x7000 0x0 0x0 0x2 &ipic 18 0x8
379 0x7000 0x0 0x0 0x3 &ipic 18 0x8
380 0x7000 0x0 0x0 0x4 &ipic 18 0x8
382 /* IDSEL 0x0F -mini PCI */
383 0x7800 0x0 0x0 0x1 &ipic 17 0x8
384 0x7800 0x0 0x0 0x2 &ipic 17 0x8
385 0x7800 0x0 0x0 0x3 &ipic 17 0x8
386 0x7800 0x0 0x0 0x4 &ipic 17 0x8
388 /* IDSEL 0x10 - PCI slot */
389 0x8000 0x0 0x0 0x1 &ipic 48 0x8
390 0x8000 0x0 0x0 0x2 &ipic 17 0x8
391 0x8000 0x0 0x0 0x3 &ipic 48 0x8
392 0x8000 0x0 0x0 0x4 &ipic 17 0x8>;
394 interrupts = <66 0x8>;
395 bus-range = <0x0 0x0>;
396 ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000
397 0x42000000 0 0x80000000 0x80000000 0 0x10000000
398 0x01000000 0 0x00000000 0xe0300000 0 0x00100000>;
403 reg = <0xe0008500 0x100 /* internal registers */
404 0xe0008300 0x8>; /* config space access registers */
415 reg = <0xe0009000 0x00001000>;
416 ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
417 0x01000000 0 0x00000000 0xb1000000 0 0x00800000>;
418 bus-range = <0 255>;
419 interrupt-map-mask = <0xf800 0 0 7>;
420 interrupt-map = <0 0 0 1 &ipic 1 8
421 0 0 0 2 &ipic 1 8
422 0 0 0 3 &ipic 1 8
423 0 0 0 4 &ipic 1 8>;
424 clock-frequency = <0>;
426 pcie@0 {
430 reg = <0 0 0 0 0>;
431 ranges = <0x02000000 0 0xa0000000
432 0x02000000 0 0xa0000000
433 0 0x10000000
434 0x01000000 0 0x00000000
435 0x01000000 0 0x00000000
436 0 0x00800000>;
446 reg = <0xe000a000 0x00001000>;
447 ranges = <0x02000000 0 0xc0000000 0xc0000000 0 0x10000000
448 0x01000000 0 0x00000000 0xd1000000 0 0x00800000>;
449 bus-range = <0 255>;
450 interrupt-map-mask = <0xf800 0 0 7>;
451 interrupt-map = <0 0 0 1 &ipic 2 8
452 0 0 0 2 &ipic 2 8
453 0 0 0 3 &ipic 2 8
454 0 0 0 4 &ipic 2 8>;
455 clock-frequency = <0>;
457 pcie@0 {
461 reg = <0 0 0 0 0>;
462 ranges = <0x02000000 0 0xc0000000
463 0x02000000 0 0xc0000000
464 0 0x10000000
465 0x01000000 0 0x00000000
466 0x01000000 0 0x00000000
467 0 0x00800000>;
475 gpios = <&mcu_pio 0 0>;
480 gpios = <&mcu_pio 1 0>;