Lines Matching +full:pcie +full:- +full:phy2
1 // SPDX-License-Identifier: GPL-2.0-or-later
9 /dts-v1/;
13 #address-cells = <1>;
14 #size-cells = <1>;
25 #address-cells = <1>;
26 #size-cells = <0>;
31 d-cache-line-size = <32>;
32 i-cache-line-size = <32>;
33 d-cache-size = <16384>;
34 i-cache-size = <16384>;
35 timebase-frequency = <0>; // from bootloader
36 bus-frequency = <0>; // from bootloader
37 clock-frequency = <0>; // from bootloader
47 #address-cells = <2>;
48 #size-cells = <1>;
49 compatible = "fsl,mpc8315-elbc", "fsl,elbc", "simple-bus";
52 interrupt-parent = <&ipic>;
63 #address-cells = <1>;
64 #size-cells = <1>;
65 compatible = "cfi-flash";
67 bank-width = <2>;
68 device-width = <1>;
70 u-boot@0 {
72 read-only;
92 #address-cells = <1>;
93 #size-cells = <1>;
94 compatible = "fsl,mpc8315-fcm-nand",
95 "fsl,elbc-fcm-nand";
105 #address-cells = <1>;
106 #size-cells = <1>;
108 compatible = "fsl,mpc8308-immr", "simple-bus";
111 bus-frequency = <0>;
114 #address-cells = <1>;
115 #size-cells = <0>;
116 cell-index = <0>;
117 compatible = "fsl-i2c";
120 interrupt-parent = <&ipic>;
129 compatible = "fsl-usb2-dr";
131 #address-cells = <1>;
132 #size-cells = <0>;
133 interrupt-parent = <&ipic>;
140 #address-cells = <1>;
141 #size-cells = <1>;
144 cell-index = <0>;
149 local-mac-address = [ 00 00 00 00 00 00 ];
151 interrupt-parent = <&ipic>;
152 tbi-handle = < &tbi0 >;
153 phy-handle = < &phy2 >;
154 fsl,magic-packet;
157 #address-cells = <1>;
158 #size-cells = <0>;
159 compatible = "fsl,gianfar-mdio";
161 phy2: ethernet-phy@2 { label
162 interrupt-parent = <&ipic>;
166 tbi0: tbi-phy@11 {
168 device_type = "tbi-phy";
174 #address-cells = <1>;
175 #size-cells = <1>;
176 cell-index = <1>;
182 local-mac-address = [ 00 00 00 00 00 00 ];
184 interrupt-parent = <&ipic>;
185 tbi-handle = < &tbi1 >;
187 fixed-link = <1 1 1000 0 0>;
188 fsl,magic-packet;
191 #address-cells = <1>;
192 #size-cells = <0>;
193 compatible = "fsl,gianfar-tbi";
196 tbi1: tbi-phy@11 {
198 device_type = "tbi-phy";
204 cell-index = <0>;
208 clock-frequency = <133333333>;
210 interrupt-parent = <&ipic>;
214 cell-index = <1>;
218 clock-frequency = <133333333>;
220 interrupt-parent = <&ipic>;
224 #gpio-cells = <2>;
226 compatible = "fsl,mpc8308-gpio", "fsl,mpc8349-gpio";
229 interrupt-parent = <&ipic>;
230 gpio-controller;
237 * sense == 2: Edge, high-to-low change
239 ipic: interrupt-controller@700 {
241 interrupt-controller;
242 #address-cells = <0>;
243 #interrupt-cells = <2>;
248 ipic-msi@7c0 {
249 compatible = "fsl,ipic-msi";
251 msi-available-ranges = <0x0 0x100>;
260 interrupt-parent = < &ipic >;
264 compatible = "fsl,mpc8308-dma";
268 interrupt-parent = < &ipic >;
273 pci0: pcie@e0009000 {
274 #address-cells = <3>;
275 #size-cells = <2>;
276 #interrupt-cells = <1>;
278 compatible = "fsl,mpc8308-pcie", "fsl,mpc8314-pcie";
283 bus-range = <0 0>;
284 interrupt-map-mask = <0xf800 0 0 7>;
285 interrupt-map = <0 0 0 1 &ipic 1 8
290 interrupt-parent = <&ipic>;
291 clock-frequency = <0>;
293 pcie@0 {
294 #address-cells = <3>;
295 #size-cells = <2>;