Lines Matching +full:io +full:- +full:channel +full:- +full:ranges
4 * Copyright 2008-2010 DENX Software Engineering, Stefan Roese <sr@denx.de>
11 /dts-v1/;
14 #address-cells = <2>;
15 #size-cells = <1>;
18 dcr-parent = <&{/cpus/cpu@0}>;
30 #address-cells = <1>;
31 #size-cells = <0>;
37 clock-frequency = <0>; /* Filled in by U-Boot */
38 timebase-frequency = <0>; /* Filled in by U-Boot */
39 i-cache-line-size = <32>;
40 d-cache-line-size = <32>;
41 i-cache-size = <32768>;
42 d-cache-size = <32768>;
43 dcr-controller;
44 dcr-access-method = "native";
45 next-level-cache = <&L2C0>;
51 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
54 UIC0: interrupt-controller0 {
55 compatible = "ibm,uic-460gt","ibm,uic";
56 interrupt-controller;
57 cell-index = <0>;
58 dcr-reg = <0x0c0 0x009>;
59 #address-cells = <0>;
60 #size-cells = <0>;
61 #interrupt-cells = <2>;
64 UIC1: interrupt-controller1 {
65 compatible = "ibm,uic-460gt","ibm,uic";
66 interrupt-controller;
67 cell-index = <1>;
68 dcr-reg = <0x0d0 0x009>;
69 #address-cells = <0>;
70 #size-cells = <0>;
71 #interrupt-cells = <2>;
73 interrupt-parent = <&UIC0>;
76 UIC2: interrupt-controller2 {
77 compatible = "ibm,uic-460gt","ibm,uic";
78 interrupt-controller;
79 cell-index = <2>;
80 dcr-reg = <0x0e0 0x009>;
81 #address-cells = <0>;
82 #size-cells = <0>;
83 #interrupt-cells = <2>;
85 interrupt-parent = <&UIC0>;
88 UIC3: interrupt-controller3 {
89 compatible = "ibm,uic-460gt","ibm,uic";
90 interrupt-controller;
91 cell-index = <3>;
92 dcr-reg = <0x0f0 0x009>;
93 #address-cells = <0>;
94 #size-cells = <0>;
95 #interrupt-cells = <2>;
97 interrupt-parent = <&UIC0>;
101 compatible = "ibm,sdr-460gt";
102 dcr-reg = <0x00e 0x002>;
106 compatible = "ibm,cpr-460gt";
107 dcr-reg = <0x00c 0x002>;
111 compatible = "ibm,l2-cache-460gt", "ibm,l2-cache";
112 dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */
114 cache-line-size = <32>; /* 32 bytes */
115 cache-size = <262144>; /* L2, 256K */
116 interrupt-parent = <&UIC1>;
121 compatible = "ibm,plb-460gt", "ibm,plb4";
122 #address-cells = <2>;
123 #size-cells = <1>;
124 ranges;
125 clock-frequency = <0>; /* Filled in by U-Boot */
128 compatible = "ibm,sdram-460gt", "ibm,sdram-405gp";
129 dcr-reg = <0x010 0x002>;
133 compatible = "amcc,ppc460gt-crypto", "amcc,ppc460ex-crypto",
134 "amcc,ppc4xx-crypto";
136 interrupt-parent = <&UIC0>;
141 compatible = "amcc,ppc460ex-rng", "ppc4xx-rng";
146 compatible = "ibm,mcmal-460gt", "ibm,mcmal2";
147 dcr-reg = <0x180 0x062>;
148 num-tx-chans = <4>;
149 num-rx-chans = <32>;
150 #address-cells = <0>;
151 #size-cells = <0>;
152 interrupt-parent = <&UIC2>;
158 desc-base-addr-high = <0x8>;
162 compatible = "ibm,opb-460gt", "ibm,opb";
163 #address-cells = <1>;
164 #size-cells = <1>;
165 ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>;
166 clock-frequency = <0>; /* Filled in by U-Boot */
169 compatible = "ibm,ebc-460gt", "ibm,ebc";
170 dcr-reg = <0x012 0x002>;
171 #address-cells = <2>;
172 #size-cells = <1>;
173 clock-frequency = <0>; /* Filled in by U-Boot */
174 /* ranges property is supplied by U-Boot */
176 interrupt-parent = <&UIC1>;
179 compatible = "amd,s29gl512n", "cfi-flash";
180 bank-width = <2>;
182 #address-cells = <1>;
183 #size-cells = <1>;
209 label = "u-boot";
218 bank-settings = <0x80002222>;
219 #address-cells = <1>;
220 #size-cells = <1>;
223 #address-cells = <1>;
224 #size-cells = <1>;
227 label = "u-boot";
242 virtual-reg = <0xef600300>;
243 clock-frequency = <0>; /* Filled in by U-Boot */
244 current-speed = <0>; /* Filled in by U-Boot */
245 interrupt-parent = <&UIC1>;
253 virtual-reg = <0xef600400>;
254 clock-frequency = <0>; /* Filled in by U-Boot */
255 current-speed = <0>; /* Filled in by U-Boot */
256 interrupt-parent = <&UIC0>;
264 virtual-reg = <0xef600500>;
265 clock-frequency = <0>; /* Filled in by U-Boot */
266 current-speed = <0>; /* Filled in by U-Boot */
267 interrupt-parent = <&UIC1>;
275 virtual-reg = <0xef600600>;
276 clock-frequency = <0>; /* Filled in by U-Boot */
277 current-speed = <0>; /* Filled in by U-Boot */
278 interrupt-parent = <&UIC1>;
283 compatible = "ibm,iic-460gt", "ibm,iic";
285 interrupt-parent = <&UIC0>;
287 #address-cells = <1>;
288 #size-cells = <0>;
292 interrupt-parent = <&UIC2>;
298 interrupt-parent = <&UIC1>;
304 compatible = "ibm,iic-460gt", "ibm,iic";
306 interrupt-parent = <&UIC0>;
310 ZMII0: emac-zmii@ef600d00 {
311 compatible = "ibm,zmii-460gt", "ibm,zmii";
315 RGMII0: emac-rgmii@ef601500 {
316 compatible = "ibm,rgmii-460gt", "ibm,rgmii";
318 has-mdio;
321 RGMII1: emac-rgmii@ef601600 {
322 compatible = "ibm,rgmii-460gt", "ibm,rgmii";
324 has-mdio;
327 TAH0: emac-tah@ef601350 {
328 compatible = "ibm,tah-460gt", "ibm,tah";
332 TAH1: emac-tah@ef601450 {
333 compatible = "ibm,tah-460gt", "ibm,tah";
339 compatible = "ibm,emac-460gt", "ibm,emac4sync";
340 interrupt-parent = <&EMAC0>;
342 #interrupt-cells = <1>;
343 #address-cells = <0>;
344 #size-cells = <0>;
345 interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4
348 local-mac-address = [000000000000]; /* Filled in by U-Boot */
349 mal-device = <&MAL0>;
350 mal-tx-channel = <0>;
351 mal-rx-channel = <0>;
352 cell-index = <0>;
353 max-frame-size = <9000>;
354 rx-fifo-size = <4096>;
355 tx-fifo-size = <2048>;
356 rx-fifo-size-gige = <16384>;
357 phy-mode = "rgmii";
358 phy-map = <0x00000000>;
359 rgmii-device = <&RGMII0>;
360 rgmii-channel = <0>;
361 tah-device = <&TAH0>;
362 tah-channel = <0>;
363 has-inverted-stacr-oc;
364 has-new-stacr-staopc;
369 compatible = "ibm,emac-460gt", "ibm,emac4sync";
370 interrupt-parent = <&EMAC1>;
372 #interrupt-cells = <1>;
373 #address-cells = <0>;
374 #size-cells = <0>;
375 interrupt-map = </*Status*/ 0x0 &UIC2 0x11 0x4
378 local-mac-address = [000000000000]; /* Filled in by U-Boot */
379 mal-device = <&MAL0>;
380 mal-tx-channel = <1>;
381 mal-rx-channel = <8>;
382 cell-index = <1>;
383 max-frame-size = <9000>;
384 rx-fifo-size = <4096>;
385 tx-fifo-size = <2048>;
386 rx-fifo-size-gige = <16384>;
387 phy-mode = "rgmii";
388 phy-map = <0x00000000>;
389 rgmii-device = <&RGMII0>;
390 rgmii-channel = <1>;
391 tah-device = <&TAH1>;
392 tah-channel = <1>;
393 has-inverted-stacr-oc;
394 has-new-stacr-staopc;
395 mdio-device = <&EMAC0>;
400 compatible = "ibm,emac-460gt", "ibm,emac4sync";
401 interrupt-parent = <&EMAC2>;
403 #interrupt-cells = <1>;
404 #address-cells = <0>;
405 #size-cells = <0>;
406 interrupt-map = </*Status*/ 0x0 &UIC2 0x12 0x4
409 local-mac-address = [000000000000]; /* Filled in by U-Boot */
410 mal-device = <&MAL0>;
411 mal-tx-channel = <2>;
412 mal-rx-channel = <16>;
413 cell-index = <2>;
414 max-frame-size = <9000>;
415 rx-fifo-size = <4096>;
416 tx-fifo-size = <2048>;
417 rx-fifo-size-gige = <16384>;
418 tx-fifo-size-gige = <16384>; /* emac2&3 only */
419 phy-mode = "rgmii";
420 phy-map = <0x00000000>;
421 rgmii-device = <&RGMII1>;
422 rgmii-channel = <0>;
423 has-inverted-stacr-oc;
424 has-new-stacr-staopc;
425 mdio-device = <&EMAC0>;
430 compatible = "ibm,emac-460gt", "ibm,emac4sync";
431 interrupt-parent = <&EMAC3>;
433 #interrupt-cells = <1>;
434 #address-cells = <0>;
435 #size-cells = <0>;
436 interrupt-map = </*Status*/ 0x0 &UIC2 0x13 0x4
439 local-mac-address = [000000000000]; /* Filled in by U-Boot */
440 mal-device = <&MAL0>;
441 mal-tx-channel = <3>;
442 mal-rx-channel = <24>;
443 cell-index = <3>;
444 max-frame-size = <9000>;
445 rx-fifo-size = <4096>;
446 tx-fifo-size = <2048>;
447 rx-fifo-size-gige = <16384>;
448 tx-fifo-size-gige = <16384>; /* emac2&3 only */
449 phy-mode = "rgmii";
450 phy-map = <0x00000000>;
451 rgmii-device = <&RGMII1>;
452 rgmii-channel = <1>;
453 has-inverted-stacr-oc;
454 has-new-stacr-staopc;
455 mdio-device = <&EMAC0>;
461 #interrupt-cells = <1>;
462 #size-cells = <2>;
463 #address-cells = <3>;
464 compatible = "ibm,plb-pcix-460gt", "ibm,plb-pcix";
466 large-inbound-windows;
467 enable-msi-hole;
474 /* Outbound ranges, one memory and one IO,
477 ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000
482 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
485 bus-range = <0x0 0x3f>;
487 /* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */
488 interrupt-map-mask = <0x0 0x0 0x0 0x0>;
489 interrupt-map = < 0x0 0x0 0x0 0x0 &UIC1 0x0 0x8 >;
494 #interrupt-cells = <1>;
495 #size-cells = <2>;
496 #address-cells = <3>;
497 compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
502 dcr-reg = <0x100 0x020>;
503 sdr-base = <0x300>;
505 /* Outbound ranges, one memory and one IO,
508 ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000
513 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
516 bus-range = <0x40 0x7f>;
520 * We are de-swizzling here because the numbers are actually for
523 * below are basically de-swizzled numbers.
526 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
527 interrupt-map = <
536 #interrupt-cells = <1>;
537 #size-cells = <2>;
538 #address-cells = <3>;
539 compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
544 dcr-reg = <0x120 0x020>;
545 sdr-base = <0x340>;
547 /* Outbound ranges, one memory and one IO,
550 ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000
555 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
558 bus-range = <0x80 0xbf>;
562 * We are de-swizzling here because the numbers are actually for
565 * below are basically de-swizzled numbers.
568 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
569 interrupt-map = <