Lines Matching +full:bman +full:- +full:fqd

4  * Copyright 2014 - 2015 Freescale Semiconductor Inc.
35 /include/ "t4240si-pre.dtsi"
40 	#address-cells = <2>;
41 	#size-cells = <2>;
42 	interrupt-parent = <&mpic>;
62 			#address-cells = <1>;
63 			#size-cells = <1>;
64 			compatible = "cfi-flash";
67 			bank-width = <2>;
68 			device-width = <1>;
72 			#address-cells = <1>;
73 			#size-cells = <1>;
74 			compatible = "fsl,ifc-nand";
83 	reserved-memory {
84 		#address-cells = <2>;
85 		#size-cells = <2>;
88 		bman_fbpr: bman-fbpr {
92 		qman_fqd: qman-fqd {
96 		qman_pfdr: qman-pfdr {
106 	bportals: bman-portals@ff4000000 {
110 	qportals: qman-portals@ff6000000 {
119 				#address-cells = <1>;
120 				#size-cells = <1>;
121 				compatible = "sst,sst25wf040", "jedec,spi-nor";
123 				spi-max-frequency = <40000000>; /* input clock */
151 			voltage-ranges = <1800 1800 3300 3300>;
156 				phy-handle = <&sgmiiphy21>;
157 				phy-connection-type = "sgmii";
161 				phy-handle = <&sgmiiphy22>;
162 				phy-connection-type = "sgmii";
166 				phy-handle = <&sgmiiphy23>;
167 				phy-connection-type = "sgmii";
171 				phy-handle = <&sgmiiphy24>;
172 				phy-connection-type = "sgmii";
184 				phy-handle = <&xfiphy1>;
185 				phy-connection-type = "xgmii";
189 				phy-handle = <&xfiphy2>;
190 				phy-connection-type = "xgmii";
196 				phy-handle = <&sgmiiphy41>;
197 				phy-connection-type = "sgmii";
201 				phy-handle = <&sgmiiphy42>;
202 				phy-connection-type = "sgmii";
206 				phy-handle = <&sgmiiphy43>;
207 				phy-connection-type = "sgmii";
211 				phy-handle = <&sgmiiphy44>;
212 				phy-connection-type = "sgmii";
224 				phy-handle = <&xfiphy3>;
225 				phy-connection-type = "xgmii";
229 				phy-handle = <&xfiphy4>;
230 				phy-connection-type = "xgmii";
234 				sgmiiphy21: ethernet-phy@0 {
238 				sgmiiphy22: ethernet-phy@1 {
242 				sgmiiphy23: ethernet-phy@2 {
246 				sgmiiphy24: ethernet-phy@3 {
250 				sgmiiphy41: ethernet-phy@4 {
254 				sgmiiphy42: ethernet-phy@5 {
258 				sgmiiphy43: ethernet-phy@6 {
262 				sgmiiphy44: ethernet-phy@7 {
268 				xfiphy1: ethernet-phy@10 {
269 					compatible = "ethernet-phy-id13e5.1002";
273 				xfiphy2: ethernet-phy@11 {
274 					compatible = "ethernet-phy-id13e5.1002";
278 				xfiphy3: ethernet-phy@13 {
279 					compatible = "ethernet-phy-id13e5.1002";
283 				xfiphy4: ethernet-phy@12 {
284 					compatible = "ethernet-phy-id13e5.1002";
363 /include/ "t4240si-post.dtsi"