Lines Matching +full:ethernet +full:- +full:phy +full:- +full:ieee802
4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
35 /include/ "t4240si-pre.dtsi"
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
89 #address-cells = <1>;
90 #size-cells = <1>;
91 compatible = "cfi-flash";
94 bank-width = <2>;
95 device-width = <1>;
99 #address-cells = <1>;
100 #size-cells = <1>;
101 compatible = "fsl,ifc-nand";
106 /* 1MB for u-boot Bootloader Image */
108 label = "NAND U-Boot Image";
109 read-only;
131 board-control@3,0 {
132 #address-cells = <1>;
133 #size-cells = <1>;
134 compatible = "fsl,t4240qds-fpga", "fsl,fpga-qixis";
138 mdio-mux-emi1 {
139 #address-cells = <1>;
140 #size-cells = <0>;
141 compatible = "mdio-mux-mmioreg", "mdio-mux";
142 mdio-parent-bus = <&mdio1>;
144 mux-mask = <0xe0>;
147 #address-cells = <1>;
148 #size-cells = <0>;
151 phyrgmii1: ethernet-phy@1 {
155 phyrgmii2: ethernet-phy@2 {
161 #address-cells = <1>;
162 #size-cells = <0>;
166 phy1: ethernet-phy@0 {
170 phy2: ethernet-phy@1 {
174 phy3: ethernet-phy@2 {
178 phy4: ethernet-phy@3 {
182 sgmiiphy11: ethernet-phy@1c {
186 sgmiiphy12: ethernet-phy@1d {
190 sgmiiphy13: ethernet-phy@1e {
194 sgmiiphy14: ethernet-phy@1f {
200 #address-cells = <1>;
201 #size-cells = <0>;
205 phy5: ethernet-phy@4 {
209 phy6: ethernet-phy@5 {
213 phy7: ethernet-phy@6 {
217 phy8: ethernet-phy@7 {
221 sgmiiphy21: ethernet-phy@1c {
225 sgmiiphy22: ethernet-phy@1d {
229 sgmiiphy23: ethernet-phy@1e {
233 sgmiiphy24: ethernet-phy@1f {
239 #address-cells = <1>;
240 #size-cells = <0>;
244 phy9: ethernet-phy@8 {
248 phy10: ethernet-phy@9 {
252 phy11: ethernet-phy@a {
256 phy12: ethernet-phy@b {
260 sgmiiphy31: ethernet-phy@1c {
264 sgmiiphy32: ethernet-phy@1d {
268 sgmiiphy33: ethernet-phy@1e {
272 sgmiiphy34: ethernet-phy@1f {
278 #address-cells = <1>;
279 #size-cells = <0>;
283 phy13: ethernet-phy@c {
287 phy14: ethernet-phy@d {
291 phy15: ethernet-phy@e {
295 phy16: ethernet-phy@f {
299 sgmiiphy41: ethernet-phy@1c {
303 sgmiiphy42: ethernet-phy@1d {
307 sgmiiphy43: ethernet-phy@1e {
311 sgmiiphy44: ethernet-phy@1f {
323 reserved-memory {
324 #address-cells = <2>;
325 #size-cells = <2>;
328 bman_fbpr: bman-fbpr {
332 qman_fqd: qman-fqd {
336 qman_pfdr: qman-pfdr {
346 bportals: bman-portals@ff4000000 {
350 qportals: qman-portals@ff6000000 {
359 #address-cells = <1>;
360 #size-cells = <1>;
361 compatible = "sst,sst25wf040", "jedec,spi-nor";
363 spi-max-frequency = <40000000>; /* input clock */
371 #address-cells = <1>;
372 #size-cells = <0>;
375 #address-cells = <1>;
376 #size-cells = <0>;
411 #address-cells = <1>;
412 #size-cells = <0>;
418 shunt-resistor = <1000>;
424 shunt-resistor = <1000>;
430 shunt-resistor = <1000>;
436 shunt-resistor = <1000>;
442 shunt-resistor = <1000>;
448 shunt-resistor = <1000>;
455 voltage-ranges = <1800 1800 3300 3300>;
479 ethernet@e0000 {
480 phy-handle = <&phy5>;
481 phy-connection-type = "sgmii";
484 ethernet@e2000 {
485 phy-handle = <&phy6>;
486 phy-connection-type = "sgmii";
489 ethernet@e4000 {
490 phy-handle = <&phy7>;
491 phy-connection-type = "sgmii";
494 ethernet@e6000 {
495 phy-handle = <&phy8>;
496 phy-connection-type = "sgmii";
499 ethernet@e8000 {
500 phy-handle = <&phyrgmii2>;
501 phy-connection-type = "rgmii";
504 ethernet@ea000 {
505 phy-handle = <&phy2>;
506 phy-connection-type = "sgmii";
509 ethernet@f0000 {
510 phy-handle = <&xauiphy1>;
511 phy-connection-type = "xgmii";
514 ethernet@f2000 {
515 phy-handle = <&xauiphy2>;
516 phy-connection-type = "xgmii";
522 xfiphy1: ethernet-phy@0 {
523 compatible = "ethernet-phy-ieee802.3-c45";
531 xfiphy2: ethernet-phy@0 {
532 compatible = "ethernet-phy-ieee802.3-c45";
555 ethernet@e0000 {
556 phy-handle = <&phy13>;
557 phy-connection-type = "sgmii";
560 ethernet@e2000 {
561 phy-handle = <&phy14>;
562 phy-connection-type = "sgmii";
565 ethernet@e4000 {
566 phy-handle = <&phy15>;
567 phy-connection-type = "sgmii";
570 ethernet@e6000 {
571 phy-handle = <&phy16>;
572 phy-connection-type = "sgmii";
575 ethernet@e8000 {
576 phy-handle = <&phyrgmii1>;
577 phy-connection-type = "rgmii";
580 ethernet@ea000 {
581 phy-handle = <&phy10>;
582 phy-connection-type = "sgmii";
585 ethernet@f0000 {
586 phy-handle = <&xauiphy3>;
587 phy-connection-type = "xgmii";
590 ethernet@f2000 {
591 phy-handle = <&xauiphy4>;
592 phy-connection-type = "xgmii";
598 xfiphy3: ethernet-phy@0 {
599 compatible = "ethernet-phy-ieee802.3-c45";
607 xfiphy4: ethernet-phy@0 {
608 compatible = "ethernet-phy-ieee802.3-c45";
614 xauiphy1: ethernet-phy@0 {
615 compatible = "ethernet-phy-ieee802.3-c45";
619 xauiphy2: ethernet-phy@1 {
620 compatible = "ethernet-phy-ieee802.3-c45";
624 xauiphy3: ethernet-phy@2 {
625 compatible = "ethernet-phy-ieee802.3-c45";
629 xauiphy4: ethernet-phy@3 {
630 compatible = "ethernet-phy-ieee802.3-c45";
708 /include/ "t4240si-post.dtsi"