Lines Matching +full:qman +full:- +full:pfdr
4 * Copyright 2013 - 2014 Freescale Semiconductor Inc.
38 #address-cells = <2>;
39 #size-cells = <2>;
40 interrupt-parent = <&mpic>;
42 reserved-memory {
43 #address-cells = <2>;
44 #size-cells = <2>;
47 bman_fbpr: bman-fbpr {
51 qman_fqd: qman-fqd {
55 qman_pfdr: qman-pfdr {
68 #address-cells = <1>;
69 #size-cells = <1>;
70 compatible = "cfi-flash";
72 bank-width = <2>;
73 device-width = <1>;
77 #address-cells = <1>;
78 #size-cells = <1>;
79 compatible = "fsl,ifc-nand";
83 boardctrl: board-control@3,0 {
84 #address-cells = <1>;
85 #size-cells = <1>;
86 compatible = "fsl,fpga-qixis";
100 bportals: bman-portals@ff4000000 {
104 qportals: qman-portals@ff6000000 {
113 #address-cells = <1>;
114 #size-cells = <1>;
115 compatible = "micron,n25q128a11", "jedec,spi-nor"; /* 16MB */
117 spi-max-frequency = <40000000>; /* input clock */
121 #address-cells = <1>;
122 #size-cells = <1>;
123 compatible = "sst,sst25wf040", "jedec,spi-nor";
125 spi-max-frequency = <35000000>;
129 #address-cells = <1>;
130 #size-cells = <1>;
131 compatible = "eon,en25s64", "jedec,spi-nor";
133 spi-max-frequency = <35000000>;
138 i2c-mux@77 {
141 #address-cells = <1>;
142 #size-cells = <0>;
145 #address-cells = <1>;
146 #size-cells = <0>;
172 #address-cells = <1>;
173 #size-cells = <0>;
183 #address-cells = <1>;
184 #size-cells = <0>;
190 shunt-resistor = <1000>;
196 shunt-resistor = <1000>;
201 #address-cells = <1>;
202 #size-cells = <0>;
214 voltage-ranges = <1800 1800 3300 3300>;