Lines Matching +full:mdio +full:- +full:mux +full:- +full:1
4 * Copyright 2013 - 2015 Freescale Semiconductor Inc.
35 /include/ "t208xsi-pre.dtsi"
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
66 phy-handle = <&phy_sgmii_s3_1e>;
67 phy-connection-type = "xgmii";
71 phy-handle = <&phy_sgmii_s3_1f>;
72 phy-connection-type = "xgmii";
76 phy-handle = <&rgmii_phy1>;
77 phy-connection-type = "rgmii";
81 phy-handle = <&rgmii_phy2>;
82 phy-connection-type = "rgmii";
86 phy-handle = <&phy_sgmii_s2_1e>;
87 phy-connection-type = "sgmii";
91 phy-handle = <&phy_sgmii_s2_1d>;
92 phy-connection-type = "sgmii";
96 phy-handle = <&phy_xaui_slot3>;
97 phy-connection-type = "xgmii";
101 phy-handle = <&phy_sgmii_s3_1f>;
102 phy-connection-type = "xgmii";
105 mdio@fd000 {
106 phy_xaui_slot3: ethernet-phy@3 {
107 compatible = "ethernet-phy-ieee802.3-c45";
115 mdio-mux-emi1 {
116 compatible = "mdio-mux-mmioreg", "mdio-mux";
117 mdio-parent-bus = <&mdio0>;
118 #address-cells = <1>;
119 #size-cells = <0>;
120 reg = <0x54 1>;
121 mux-mask = <0xe0>;
123 t2080mdio0: mdio@0 {
124 #address-cells = <1>;
125 #size-cells = <0>;
128 rgmii_phy1: ethernet-phy@1 {
133 t2080mdio1: mdio@20 {
134 #address-cells = <1>;
135 #size-cells = <0>;
138 rgmii_phy2: ethernet-phy@2 {
143 t2080mdio2: mdio@40 {
144 #address-cells = <1>;
145 #size-cells = <0>;
149 phy_sgmii_s1_1c: ethernet-phy@1c {
153 phy_sgmii_s1_1d: ethernet-phy@1d {
157 phy_sgmii_s1_1e: ethernet-phy@1e {
161 phy_sgmii_s1_1f: ethernet-phy@1f {
166 t2080mdio3: mdio@c0 {
167 #address-cells = <1>;
168 #size-cells = <0>;
171 phy_sgmii_s2_1c: ethernet-phy@1c {
175 phy_sgmii_s2_1d: ethernet-phy@1d {
179 phy_sgmii_s2_1e: ethernet-phy@1e {
183 phy_sgmii_s2_1f: ethernet-phy@1f {
188 t2080mdio4: mdio@60 {
189 #address-cells = <1>;
190 #size-cells = <0>;
194 phy_sgmii_s3_1c: ethernet-phy@1c {
198 phy_sgmii_s3_1d: ethernet-phy@1d {
202 phy_sgmii_s3_1e: ethernet-phy@1e {
206 phy_sgmii_s3_1f: ethernet-phy@1f {
213 /include/ "t2080si-post.dtsi"