Lines Matching +full:qman +full:- +full:pfdr
35 /include/ "t102xsi-pre.dtsi"
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
48 reserved-memory {
49 #address-cells = <2>;
50 #size-cells = <2>;
53 bman_fbpr: bman-fbpr {
58 qman_fqd: qman-fqd {
63 qman_pfdr: qman-pfdr {
76 #address-cells = <1>;
77 #size-cells = <1>;
78 compatible = "cfi-flash";
80 bank-width = <2>;
81 device-width = <1>;
85 #address-cells = <1>;
86 #size-cells = <1>;
87 compatible = "fsl,ifc-nand";
91 board-control@2,0 {
92 #address-cells = <1>;
93 #size-cells = <1>;
94 compatible = "fsl,t1024-cpld", "fsl,deepsleep-cpld";
97 bank-width = <1>;
98 device-width = <1>;
110 bportals: bman-portals@ff4000000 {
114 qportals: qman-portals@ff6000000 {
123 #address-cells = <1>;
124 #size-cells = <1>;
125 compatible = "micron,n25q512ax3", "jedec,spi-nor";
127 spi-max-frequency = <10000000>; /* input clk */
133 spi-max-frequency = <2000000>;
139 spi-max-frequency = <2000000>;
150 current-sensor@40 {
153 shunt-resistor = <1000>;
168 i2c-mux@77 {
171 #address-cells = <1>;
172 #size-cells = <0>;
178 phy-handle = <&xg_aqr105_phy3>;
179 phy-connection-type = "xgmii";
188 phy-handle = <&rgmii_phy2>;
189 phy-connection-type = "rgmii";
194 phy-handle = <&rgmii_phy1>;
195 phy-connection-type = "rgmii";
201 rgmii_phy1: ethernet-phy@2 {
204 rgmii_phy2: ethernet-phy@6 {
210 xg_aqr105_phy3: ethernet-phy@1 {
211 compatible = "ethernet-phy-ieee802.3-c45";
214 sg_2500_aqr105_phy4: ethernet-phy@2 {
215 compatible = "ethernet-phy-ieee802.3-c45";
268 #include "t1024si-post.dtsi"