Lines Matching +full:qman +full:- +full:pfdr
4 * Copyright 2010 - 2015 Freescale Semiconductor Inc.
35 /include/ "p5020si-pre.dtsi"
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
62 reserved-memory {
63 #address-cells = <2>;
64 #size-cells = <2>;
67 bman_fbpr: bman-fbpr {
71 qman_fqd: qman-fqd {
75 qman_pfdr: qman-pfdr {
85 bportals: bman-portals@ff4000000 {
89 qportals: qman-portals@ff4200000 {
98 #address-cells = <1>;
99 #size-cells = <1>;
100 compatible = "spansion,s25sl12801", "jedec,spi-nor";
102 spi-max-frequency = <40000000>; /* input clock */
103 partition@u-boot {
104 label = "u-boot";
106 read-only;
111 read-only;
116 read-only;
145 shunt-resistor = <1000>;
150 shunt-resistor = <1000>;
155 shunt-resistor = <1000>;
160 shunt-resistor = <1000>;
170 phy-handle = <&phy_sgmii_1c>;
171 phy-connection-type = "sgmii";
175 phy-handle = <&phy_sgmii_1d>;
176 phy-connection-type = "sgmii";
180 phy-handle = <&phy_sgmii_1e>;
181 phy-connection-type = "sgmii";
185 phy-handle = <&phy_sgmii_1f>;
186 phy-connection-type = "sgmii";
190 phy-handle = <&phy_rgmii_1>;
191 phy-connection-type = "rgmii";
195 phy-handle = <&phy_xgmii_1>;
196 phy-connection-type = "xgmii";
202 phy_xgmii_1: ethernet-phy@4 {
203 compatible = "ethernet-phy-ieee802.3-c45";
207 phy_xgmii_2: ethernet-phy@0 {
208 compatible = "ethernet-phy-ieee802.3-c45";
233 compatible = "cfi-flash";
235 bank-width = <2>;
236 device-width = <2>;
240 #address-cells = <1>;
241 #size-cells = <1>;
242 compatible = "fsl,elbc-fcm-nand";
246 label = "NAND U-Boot Image";
248 read-only;
277 board-control@3,0 {
278 #address-cells = <1>;
279 #size-cells = <1>;
280 compatible = "fsl,p5020ds-fpga", "fsl,fpga-ngpixis";
284 mdio-mux-emi1 {
285 #address-cells = <1>;
286 #size-cells = <0>;
287 compatible = "mdio-mux-mmioreg", "mdio-mux";
288 mdio-parent-bus = <&mdio0>;
290 mux-mask = <0x78>;
292 hydra_mdio_rgmii: rgmii-mdio@8 {
293 #address-cells = <1>;
294 #size-cells = <0>;
298 phy_rgmii_0: ethernet-phy@0 {
302 phy_rgmii_1: ethernet-phy@1 {
307 hydra_mdio_sgmii: sgmii-mdio@28 {
308 #address-cells = <1>;
309 #size-cells = <0>;
313 phy_sgmii_1c: ethernet-phy@1c {
317 phy_sgmii_1d: ethernet-phy@1d {
321 phy_sgmii_1e: ethernet-phy@1e {
325 phy_sgmii_1f: ethernet-phy@1f {
394 /include/ "p5020si-post.dtsi"