Lines Matching +full:pcie +full:- +full:phy2
4 * Copyright 2009 - 2015 Freescale Semiconductor Inc.
35 /include/ "p4080si-pre.dtsi"
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
62 reserved-memory {
63 #address-cells = <2>;
64 #size-cells = <2>;
67 bman_fbpr: bman-fbpr {
71 qman_fqd: qman-fqd {
75 qman_pfdr: qman-pfdr {
85 bportals: bman-portals@ff4000000 {
89 qportals: qman-portals@ff4200000 {
99 #address-cells = <1>;
100 #size-cells = <1>;
101 compatible = "spansion,s25sl12801", "jedec,spi-nor";
103 spi-max-frequency = <40000000>; /* input clock */
104 partition@u-boot {
105 label = "u-boot";
107 read-only;
112 read-only;
117 read-only;
196 phy-handle = <&phy0>;
197 phy-connection-type = "sgmii";
201 phy-handle = <&phy1>;
202 phy-connection-type = "sgmii";
206 phy-handle = <&phy2>;
207 phy-connection-type = "sgmii";
211 phy-handle = <&phy3>;
212 phy-connection-type = "sgmii";
216 phy-handle = <&phy10>;
217 phy-connection-type = "xgmii";
223 phy-handle = <&phy5>;
224 phy-connection-type = "sgmii";
228 phy-handle = <&phy6>;
229 phy-connection-type = "sgmii";
233 phy-handle = <&phy7>;
234 phy-connection-type = "sgmii";
238 phy-handle = <&phy8>;
239 phy-connection-type = "sgmii";
243 phy-handle = <&phy11>;
244 phy-connection-type = "xgmii";
266 compatible = "cfi-flash";
268 bank-width = <2>;
269 device-width = <2>;
272 board-control@3,0 {
273 compatible = "fsl,p4080ds-fpga", "fsl,fpga-ngpixis";
278 pci0: pcie@ffe200000 {
282 pcie@0 {
293 pci1: pcie@ffe201000 {
297 pcie@0 {
308 pci2: pcie@ffe202000 {
312 pcie@0 {
323 mdio-mux-emi1 {
324 #address-cells = <1>;
325 #size-cells = <0>;
326 compatible = "mdio-mux-gpio", "mdio-mux";
327 mdio-parent-bus = <&mdio0>;
331 #address-cells = <1>;
332 #size-cells = <0>;
335 phyrgmii: ethernet-phy@0 {
341 #address-cells = <1>;
342 #size-cells = <0>;
345 phy5: ethernet-phy@1c {
349 phy6: ethernet-phy@1d {
353 phy7: ethernet-phy@1e {
357 phy8: ethernet-phy@1f {
363 #address-cells = <1>;
364 #size-cells = <0>;
368 phy5slot3: ethernet-phy@1c {
372 phy6slot3: ethernet-phy@1d {
376 phy7slot3: ethernet-phy@1e {
380 phy8slot3: ethernet-phy@1f {
386 #address-cells = <1>;
387 #size-cells = <0>;
390 phy0: ethernet-phy@1c {
394 phy1: ethernet-phy@1d {
398 phy2: ethernet-phy@1e { label
402 phy3: ethernet-phy@1f {
408 mdio-mux-emi2 {
409 #address-cells = <1>;
410 #size-cells = <0>;
411 compatible = "mdio-mux-gpio", "mdio-mux";
412 mdio-parent-bus = <&xmdio0>;
416 #address-cells = <1>;
417 #size-cells = <0>;
420 phy11: ethernet-phy@0 {
421 compatible = "ethernet-phy-ieee802.3-c45";
427 #address-cells = <1>;
428 #size-cells = <0>;
431 phy10: ethernet-phy@4 {
432 compatible = "ethernet-phy-ieee802.3-c45";
439 /include/ "p4080si-post.dtsi"