Lines Matching +full:0 +full:x12000000
68 size = <0 0x1000000>;
69 alignment = <0 0x1000000>;
72 size = <0 0x400000>;
73 alignment = <0 0x400000>;
76 size = <0 0x2000000>;
77 alignment = <0 0x2000000>;
82 ranges = <0x00000000 0xf 0x00000000 0x01008000>;
86 ranges = <0x0 0xf 0xf4000000 0x200000>;
90 ranges = <0x0 0xf 0xf4200000 0x200000>;
94 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
95 reg = <0xf 0xfe000000 0 0x00001000>;
97 flash@0 {
101 reg = <0>;
105 reg = <0x00000000 0x00100000>;
110 reg = <0x00100000 0x00500000>;
115 reg = <0x00600000 0x00100000>;
120 reg = <0x00700000 0x00900000>;
128 reg = <0x51>;
132 reg = <0x52>;
139 reg = <0x68>;
140 interrupts = <0x1 0x1 0 0>;
144 reg = <0x40>;
149 reg = <0x41>;
154 reg = <0x44>;
159 reg = <0x45>;
164 reg = <0x4c>;
204 reg = <0x4>;
207 phy_xgmii_2: ethernet-phy@0 {
209 reg = <0x0>;
216 reg = <0xf 0xfe0c0000 0 0x11000>;
219 ranges = <0 0 0xc 0x20000000 0 0x10000000>;
222 ranges = <0 0 0xc 0x30000000 0 0x10000000>;
227 reg = <0xf 0xfe124000 0 0x1000>;
228 ranges = <0 0 0xf 0xe8000000 0x08000000
229 2 0 0xf 0xffa00000 0x00040000
230 3 0 0xf 0xffdf0000 0x00008000>;
232 flash@0,0 {
234 reg = <0 0 0x08000000>;
239 nand@2,0 {
243 reg = <0x2 0x0 0x40000>;
245 partition@0 {
247 reg = <0x0 0x02000000>;
253 reg = <0x02000000 0x10000000>;
258 reg = <0x12000000 0x08000000>;
263 reg = <0x1a000000 0x04000000>;
268 reg = <0x1e000000 0x01000000>;
273 reg = <0x1f000000 0x21000000>;
277 board-control@3,0 {
281 reg = <3 0 0x30>;
282 ranges = <0 3 0 0x30>;
286 #size-cells = <0>;
290 mux-mask = <0x78>;
294 #size-cells = <0>;
298 phy_rgmii_0: ethernet-phy@0 {
299 reg = <0x0>;
303 reg = <0x1>;
309 #size-cells = <0>;
310 reg = <0x28>;
314 reg = <0x1c>;
318 reg = <0x1d>;
322 reg = <0x1e>;
326 reg = <0x1f>;
334 reg = <0xf 0xfe200000 0 0x1000>;
335 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
336 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
337 pcie@0 {
338 ranges = <0x02000000 0 0xe0000000
339 0x02000000 0 0xe0000000
340 0 0x20000000
342 0x01000000 0 0x00000000
343 0x01000000 0 0x00000000
344 0 0x00010000>;
349 reg = <0xf 0xfe201000 0 0x1000>;
350 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
351 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
352 pcie@0 {
353 ranges = <0x02000000 0 0xe0000000
354 0x02000000 0 0xe0000000
355 0 0x20000000
357 0x01000000 0 0x00000000
358 0x01000000 0 0x00000000
359 0 0x00010000>;
364 reg = <0xf 0xfe202000 0 0x1000>;
365 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
366 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
367 pcie@0 {
368 ranges = <0x02000000 0 0xe0000000
369 0x02000000 0 0xe0000000
370 0 0x20000000
372 0x01000000 0 0x00000000
373 0x01000000 0 0x00000000
374 0 0x00010000>;
379 reg = <0xf 0xfe203000 0 0x1000>;
380 ranges = <0x02000000 0 0xe0000000 0xc 0x60000000 0 0x20000000
381 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
382 pcie@0 {
383 ranges = <0x02000000 0 0xe0000000
384 0x02000000 0 0xe0000000
385 0 0x20000000
387 0x01000000 0 0x00000000
388 0x01000000 0 0x00000000
389 0 0x00010000>;