Lines Matching +full:qman +full:- +full:pfdr

4  * Copyright 2011 - 2015 Freescale Semiconductor Inc.
35 /include/ "p2041si-pre.dtsi"
40 	#address-cells = <2>;
41 	#size-cells = <2>;
42 	interrupt-parent = <&mpic>;
61 	reserved-memory {
62 		#address-cells = <2>;
63 		#size-cells = <2>;
66 		bman_fbpr: bman-fbpr {
70 		qman_fqd: qman-fqd {
74 		qman_pfdr: qman-pfdr {
84 	bportals: bman-portals@ff4000000 {
88 	qportals: qman-portals@ff4200000 {
97 				#address-cells = <1>;
98 				#size-cells = <1>;
99 				compatible = "spansion,s25sl12801", "jedec,spi-nor";
101 				spi-max-frequency = <40000000>; /* input clock */
102 				partition@u-boot {
103 					label = "u-boot";
105 					read-only;
110 					read-only;
115 					read-only;
156 				phy-handle = <&phy_sgmii_2>;
157 				phy-connection-type = "sgmii";
161 				phy_rgmii_0: ethernet-phy@0 {
165 				phy_rgmii_1: ethernet-phy@1 {
169 				phy_sgmii_2: ethernet-phy@2 {
173 				phy_sgmii_3: ethernet-phy@3 {
177 				phy_sgmii_4: ethernet-phy@4 {
181 				phy_sgmii_1c: ethernet-phy@1c {
185 				phy_sgmii_1d: ethernet-phy@1d {
189 				phy_sgmii_1e: ethernet-phy@1e {
193 				phy_sgmii_1f: ethernet-phy@1f {
199 				phy-handle = <&phy_sgmii_3>;
200 				phy-connection-type = "sgmii";
204 				phy-handle = <&phy_sgmii_4>;
205 				phy-connection-type = "sgmii";
209 				phy-handle = <&phy_rgmii_1>;
210 				phy-connection-type = "rgmii";
214 				phy-handle = <&phy_rgmii_0>;
215 				phy-connection-type = "rgmii";
219 				phy-handle = <&phy_xgmii_2>;
220 				phy-connection-type = "xgmii";
224 				phy_xgmii_2: ethernet-phy@0 {
225 					compatible = "ethernet-phy-ieee802.3-c45";
249 			compatible = "cfi-flash";
251 			bank-width = <2>;
252 			device-width = <2>;
256 			#address-cells = <1>;
257 			#size-cells = <1>;
258 			compatible = "fsl,elbc-fcm-nand";
262 				label = "NAND U-Boot Image";
264 				read-only;
340 /include/ "p2041si-post.dtsi"