Lines Matching +full:0 +full:x1e000000
67 size = <0 0x1000000>;
68 alignment = <0 0x1000000>;
71 size = <0 0x400000>;
72 alignment = <0 0x400000>;
75 size = <0 0x2000000>;
76 alignment = <0 0x2000000>;
81 ranges = <0x00000000 0xf 0x00000000 0x01008000>;
85 ranges = <0x0 0xf 0xf4000000 0x200000>;
89 ranges = <0x0 0xf 0xf4200000 0x200000>;
93 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
94 reg = <0xf 0xfe000000 0 0x00001000>;
96 flash@0 {
100 reg = <0>;
104 reg = <0x00000000 0x00100000>;
109 reg = <0x00100000 0x00500000>;
114 reg = <0x00600000 0x00100000>;
119 reg = <0x00700000 0x00900000>;
127 reg = <0x48>;
131 reg = <0x50>;
135 reg = <0x68>;
139 reg = <0x4c>;
146 reg = <0x50>;
161 phy_rgmii_0: ethernet-phy@0 {
162 reg = <0x0>;
166 reg = <0x1>;
170 reg = <0x2>;
174 reg = <0x3>;
178 reg = <0x4>;
182 reg = <0x1c>;
186 reg = <0x1d>;
190 reg = <0x1e>;
194 reg = <0x1f>;
224 phy_xgmii_2: ethernet-phy@0 {
226 reg = <0x0>;
233 reg = <0xf 0xfe0c0000 0 0x11000>;
236 ranges = <0 0 0xc 0x20000000 0 0x10000000>;
239 ranges = <0 0 0xc 0x30000000 0 0x10000000>;
244 reg = <0xf 0xfe124000 0 0x1000>;
245 ranges = <0 0 0xf 0xe8000000 0x08000000
246 1 0 0xf 0xffa00000 0x00040000>;
248 flash@0,0 {
250 reg = <0 0 0x08000000>;
255 nand@1,0 {
259 reg = <0x1 0x0 0x40000>;
261 partition@0 {
263 reg = <0x0 0x02000000>;
269 reg = <0x02000000 0x10000000>;
274 reg = <0x12000000 0x08000000>;
279 reg = <0x1a000000 0x04000000>;
284 reg = <0x1e000000 0x01000000>;
289 reg = <0x1f000000 0x01000000>;
295 reg = <0xf 0xfe200000 0 0x1000>;
296 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
297 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
298 pcie@0 {
299 ranges = <0x02000000 0 0xe0000000
300 0x02000000 0 0xe0000000
301 0 0x20000000
303 0x01000000 0 0x00000000
304 0x01000000 0 0x00000000
305 0 0x00010000>;
310 reg = <0xf 0xfe201000 0 0x1000>;
311 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
312 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
313 pcie@0 {
314 ranges = <0x02000000 0 0xe0000000
315 0x02000000 0 0xe0000000
316 0 0x20000000
318 0x01000000 0 0x00000000
319 0x01000000 0 0x00000000
320 0 0x00010000>;
325 reg = <0xf 0xfe202000 0 0x1000>;
326 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
327 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
328 pcie@0 {
329 ranges = <0x02000000 0 0xe0000000
330 0x02000000 0 0xe0000000
331 0 0x20000000
333 0x01000000 0 0x00000000
334 0x01000000 0 0x00000000
335 0 0x00010000>;