Lines Matching +full:fpga +full:- +full:1

1 // SPDX-License-Identifier: GPL-2.0-or-later
14  * Compiled with dtc -I dts -O dtb -o gef_sbc310.dtb gef_sbc310.dts
17 /include/ "mpc8641si-pre.dtsi"
32 			  1 0 0xe0000000 0x08000000	// Paged Flash 0
33 			  2 0 0xe8000000 0x08000000	// Paged Flash 1
35 			  4 0 0xfc000000 0x00010000>;	// FPGA
37 		/* flash@0,0 is a mirror of part of the memory in flash@1,0
39 			compatible = "gef,sbc310-firmware-mirror", "cfi-flash";
41 			bank-width = <2>;
42 			device-width = <2>;
43 			#address-cells = <1>;
44 			#size-cells = <1>;
48 				read-only;
53 		flash@1,0 {
54 			compatible = "gef,sbc310-paged-flash", "cfi-flash";
56 			bank-width = <2>;
57 			device-width = <2>;
58 			#address-cells = <1>;
59 			#size-cells = <1>;
67 				read-only;
77 		fpga@4,0 {
78 			compatible = "gef,fpga-regs";
83 			compatible = "gef,sbc310-fpga-wdt", "gef,fpga-wdt-1.00",
84 				"gef,fpga-wdt";
87 			interrupt-parent = <&gef_pic>;
91 			compatible = "gef,sbc310-fpga-wdt", "gef,fpga-wdt-1.00",
92 				"gef,fpga-wdt";
95 			interrupt-parent = <&gef_pic>;
99 			#interrupt-cells = <1>;
100 			interrupt-controller;
101 			compatible = "gef,sbc310-fpga-pic", "gef,fpga-pic";
107 			#gpio-cells = <2>;
108 			compatible = "gef,sbc310-gpio";
110 			gpio-controller;
142 			tbi-handle = <&tbi0>;
143 			phy-handle = <&phy0>;
144 			phy-connection-type = "gmii";
148 			phy0: ethernet-phy@0 {
149 				interrupt-parent = <&gef_pic>;
151 				reg = <1>;
153 			phy2: ethernet-phy@2 {
154 				interrupt-parent = <&gef_pic>;
158 			tbi0: tbi-phy@11 {
160 				device_type = "tbi-phy";
165 			tbi-handle = <&tbi2>;
166 			phy-handle = <&phy2>;
167 			phy-connection-type = "gmii";
171 			tbi2: tbi-phy@11 {
173 				device_type = "tbi-phy";
198 		interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
199 		interrupt-map = <
234 /include/ "mpc8641si-post.dtsi"