Lines Matching +full:qman +full:- +full:pfdr

4  * Copyright 2012 - 2015 Freescale Semiconductor, Inc.
38 	#address-cells = <2>;
39 	#size-cells = <2>;
40 	interrupt-parent = <&mpic>;
57 			#address-cells = <1>;
58 			#size-cells = <1>;
59 			compatible = "cfi-flash";
61 			bank-width = <2>;
62 			device-width = <1>;
66 			#address-cells = <1>;
67 			#size-cells = <1>;
68 			compatible = "fsl,ifc-nand";
73 				/* 1MB for u-boot Bootloader Image */
75 				label = "NAND U-Boot Image";
76 				read-only;
98 		board-control@3,0 {
99 			compatible = "fsl,b4qds-fpga", "fsl,fpga-qixis";
108 	reserved-memory {
109 		#address-cells = <2>;
110 		#size-cells = <2>;
113 		bman_fbpr: bman-fbpr {
117 		qman_fqd: qman-fqd {
121 		qman_pfdr: qman-pfdr {
131 	bportals: bman-portals@ff4000000 {
135 	qportals: qman-portals@ff6000000 {
144 				#address-cells = <1>;
145 				#size-cells = <1>;
146 				compatible = "sst,sst25wf040", "jedec,spi-nor";
148 				spi-max-frequency = <40000000>; /* input clock */
161 				#address-cells = <1>;
162 				#size-cells = <0>;
165 					#address-cells = <1>;
166 					#size-cells = <0>;
192 					#address-cells = <1>;
193 					#size-cells = <0>;
199 						shunt-resistor = <1000>;
204 					#address-cells = <1>;
205 					#size-cells = <0>;
223 				phy-handle = <&phy_sgmii_10>;
224 				phy-connection-type = "sgmii";
228 				phy-handle = <&phy_sgmii_11>;
229 				phy-connection-type = "sgmii";
233 				phy-handle = <&phy_sgmii_1c>;
234 				phy-connection-type = "sgmii";
238 				phy-handle = <&phy_sgmii_1d>;
239 				phy-connection-type = "sgmii";
243 				phy_sgmii_10: ethernet-phy@10 {
247 				phy_sgmii_11: ethernet-phy@11 {
251 				phy_sgmii_1c: ethernet-phy@1c {
256 				phy_sgmii_1d: ethernet-phy@1d {
280 /include/ "b4si-post.dtsi"