Lines Matching +full:ethernet +full:- +full:phy +full:- +full:ieee802
4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
35 /include/ "b4860si-pre.dtsi"
50 board-control@3,0 {
51 compatible = "fsl,b4860qds-fpga", "fsl,fpga-qixis";
57 ethernet@e8000 {
58 phy-handle = <&phy_sgmii_1e>;
59 phy-connection-type = "sgmii";
62 ethernet@ea000 {
63 phy-handle = <&phy_sgmii_1f>;
64 phy-connection-type = "sgmii";
67 ethernet@f0000 {
68 phy-handle = <&phy_xaui_slot1>;
69 phy-connection-type = "xgmii";
72 ethernet@f2000 {
73 phy-handle = <&phy_xaui_slot2>;
74 phy-connection-type = "xgmii";
78 phy_sgmii_1e: ethernet-phy@1e {
83 phy_sgmii_1f: ethernet-phy@1f {
90 phy_xaui_slot1: xaui-phy@slot1 {
91 compatible = "ethernet-phy-ieee802.3-c45";
96 phy_xaui_slot2: xaui-phy@slot2 {
97 compatible = "ethernet-phy-ieee802.3-c45";
117 /include/ "b4860si-post.dtsi"