Lines Matching +full:0 +full:x01f00000
14 /memreserve/ 0x01f00000 0x00100000; // spin table
21 dcr-parent = <&{/cpus/cpu@0}>;
29 #size-cells = <0>;
31 cpu@0 {
34 reg = <0>;
59 cpu-release-addr = <0x0 0x01f00000>;
65 reg = <0x0 0x0 0x0 0x0>; // filled in by zImage
71 dcr-reg = <0xffc00000 0x00040000>;
72 #address-cells = <0>;
73 #size-cells = <0>;
87 reg = <0x310 0x000e0000 0x0 0xf0>;
89 interrupts = <108 0
90 109 0
91 110 0
92 111 0
93 112 0
94 113 0
95 114 0
96 115 0
97 116 0
98 117 0
99 118 0
100 119 0
101 120 0
102 121 0
103 122 0
104 123 0>;
109 dcr-reg = <0xc0000000 0x062>;
112 #address-cells = <0>;
113 #size-cells = <0>;
115 interrupts = < /*TXEOB*/ 77 0x4
116 /*RXEOB*/ 78 0x4
117 /*SERR*/ 76 0x4
118 /*TXDE*/ 79 0x4
119 /*RXDE*/ 80 0x4>;
124 reg = <0x300 0x00010000 0x0 0x10000>;
131 reg = <0x300 0x10000000 0x0 0x10000>;
138 reg = <0x300 0x00000000 0x0 0x10000>;
145 reg = <0x300 0x10010000 0x0 0x10000>;
152 reg = <0x300 0x10020000 0x0 0x10000>;
164 ranges = <0x00000000 0x0000033f 0x00000000 0x80000000
165 0x80000000 0x0000033f 0x80000000 0x80000000>;
170 reg = <0x50004 0x00000008>;
178 interrupts = <0x0 0x1>;
180 #address-cells = <0>;
181 #size-cells = <0>;
182 interrupt-map = </*Status*/ 0x0 &MPIC 81 0x4
183 /*Wake*/ 0x1 &MPIC 82 0x4>;
184 reg = <0x30000 0x78>;
194 mal-tx-channel = <0>;
195 mal-rx-channel = <0>;
196 cell-index = <0>;
202 phy-map = <0x00000000>;
211 reg = <0x10000 0x00000008>;
212 virtual-reg = <0xe8010000>;
219 IIC0: i2c@0 {
221 reg = <0x0 0x00000020>;
225 #size-cells = <0>;
228 reg = <0x68>;
234 reg = <0x100 0x00000020>;
238 #size-cells = <0>;
241 reg = <0x58>;
247 reg = <0xebc00000 0x8>;
258 port = <0x0>; /* port number */
259 reg = <0x00000101 0x00000000 0x0 0x10000000 /* Config space access */
260 0x00000100 0x00000000 0x0 0x00001000>; /* UTL Registers space access */
261 dcr-reg = <0xc0 0x20>;
264 ranges = <0x02000000 0x00000000 0x80000000 0x00000110 0x80000000 0x0 0x80000000
265 0x01000000 0x0 0x0 0x00000140 0x0 0x0 0x00010000>;
267 /* Inbound starting at 0x0 to 0x40000000000. In order to use MSI
270 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x400 0x0>;
272 /* This drives busses 0 to 0xf */
273 bus-range = <0x0 0xf>;
281 * The real slot is on idsel 0, so the swizzling is 1:1
283 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
285 0x0 0x0 0x0 0x1 &MPIC 45 0x2 /* int A */
286 0x0 0x0 0x0 0x2 &MPIC 46 0x2 /* int B */
287 0x0 0x0 0x0 0x3 &MPIC 47 0x2 /* int C */
288 0x0 0x0 0x0 0x4 &MPIC 48 0x2 /* int D */>;
298 port = <0x1>; /* port number */
299 reg = <0x00000201 0x00000000 0x0 0x10000000 /* Config space access */
300 0x00000200 0x00000000 0x0 0x00001000>; /* UTL Registers space access */
301 dcr-reg = <0x100 0x20>;
304 ranges = <0x02000000 0x00000000 0x80000000 0x00000210 0x80000000 0x0 0x80000000
305 0x01000000 0x0 0x0 0x00000240 0x0 0x0 0x00010000>;
307 /* Inbound starting at 0x0 to 0x40000000000. In order to use MSI
310 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x400 0x0>;
312 /* This drives busses 0 to 0xf */
313 bus-range = <0x0 0xf>;
321 * The real slot is on idsel 0, so the swizzling is 1:1
323 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
325 0x0 0x0 0x0 0x1 &MPIC 53 0x2 /* int A */
326 0x0 0x0 0x0 0x2 &MPIC 54 0x2 /* int B */
327 0x0 0x0 0x0 0x3 &MPIC 55 0x2 /* int C */
328 0x0 0x0 0x0 0x4 &MPIC 56 0x2 /* int D */>;
338 port = <0x2>; /* port number */
339 reg = <0x00000181 0x00000000 0x0 0x10000000 /* Config space access */
340 0x00000180 0x00000000 0x0 0x00001000>; /* UTL Registers space access */
341 dcr-reg = <0xe0 0x20>;
344 ranges = <0x02000000 0x00000000 0x80000000 0x00000190 0x80000000 0x0 0x80000000
345 0x01000000 0x0 0x0 0x000001c0 0x0 0x0 0x00010000>;
347 /* Inbound starting at 0x0 to 0x40000000000. In order to use MSI
350 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x400 0x0>;
352 /* This drives busses 0 to 0xf */
353 bus-range = <0x0 0xf>;
361 * The real slot is on idsel 0, so the swizzling is 1:1
363 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
365 0x0 0x0 0x0 0x1 &MPIC 61 0x2 /* int A */
366 0x0 0x0 0x0 0x2 &MPIC 62 0x2 /* int B */
367 0x0 0x0 0x0 0x3 &MPIC 63 0x2 /* int C */
368 0x0 0x0 0x0 0x4 &MPIC 64 0x2 /* int D */>;
378 port = <0x3>; /* port number */
379 reg = <0x00000281 0x00000000 0x0 0x10000000 /* Config space access */
380 0x00000280 0x00000000 0x0 0x00001000>; /* UTL Registers space access */
381 dcr-reg = <0x120 0x20>;
384 ranges = <0x02000000 0x00000000 0x80000000 0x00000290 0x80000000 0x0 0x80000000
385 0x01000000 0x0 0x0 0x000002c0 0x0 0x0 0x00010000>;
387 /* Inbound starting at 0x0 to 0x40000000000. In order to use MSI
390 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x400 0x0>;
392 /* This drives busses 0 to 0xf */
393 bus-range = <0x0 0xf>;
401 * The real slot is on idsel 0, so the swizzling is 1:1
403 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
405 0x0 0x0 0x0 0x1 &MPIC 69 0x2 /* int A */
406 0x0 0x0 0x0 0x2 &MPIC 70 0x2 /* int B */
407 0x0 0x0 0x0 0x3 &MPIC 71 0x2 /* int C */
408 0x0 0x0 0x0 0x4 &MPIC 72 0x2 /* int D */>;