Lines Matching +full:0 +full:x00018000
8 asm volatile("mfdcr %0,%1" : "=r"(rval) : "i"(rn)); \
12 asm volatile("mtdcr %0,%1" : : "i"(rn), "r"(val))
16 asm volatile("mfdcrx %0,%1" : "=r"(rval) : "r"(rn)); \
21 asm volatile("mtdcrx %0,%1" : : "r"(rn), "r" (val)); \
25 #define DCRN_SDRAM0_CFGADDR 0x010
26 #define DCRN_SDRAM0_CFGDATA 0x011
35 #define SDRAM0_B0CR 0x40
36 #define SDRAM0_B1CR 0x44
37 #define SDRAM0_B2CR 0x48
38 #define SDRAM0_B3CR 0x4c
43 #define SDRAM_CONFIG_BANK_ENABLE 0x00000001
44 #define SDRAM_CONFIG_SIZE_MASK 0x000e0000
46 (0x00400000 << ((reg & SDRAM_CONFIG_SIZE_MASK) >> 17))
49 #define DCRN_EBC0_CFGADDR 0x012
50 #define DCRN_EBC0_CFGDATA 0x013
52 #define EBC_B0CR 0x00
53 #define EBC_B1CR 0x01
54 #define EBC_B2CR 0x02
55 #define EBC_B3CR 0x03
56 #define EBC_B4CR 0x04
57 #define EBC_B5CR 0x05
58 #define EBC_B6CR 0x06
59 #define EBC_B7CR 0x07
61 #define EBC_BXCR_BAS 0xfff00000
62 #define EBC_BXCR_BS 0x000e0000
64 (0x100000 << (((reg) & EBC_BXCR_BS) >> 17))
65 #define EBC_BXCR_BU 0x00018000
66 #define EBC_BXCR_BU_OFF 0x00000000
67 #define EBC_BXCR_BU_RO 0x00008000
68 #define EBC_BXCR_BU_WO 0x00010000
69 #define EBC_BXCR_BU_RW 0x00018000
70 #define EBC_BXCR_BW 0x00006000
71 #define EBC_B0AP 0x10
72 #define EBC_B1AP 0x11
73 #define EBC_B2AP 0x12
74 #define EBC_B3AP 0x13
75 #define EBC_B4AP 0x14
76 #define EBC_B5AP 0x15
77 #define EBC_B6AP 0x16
78 #define EBC_B7AP 0x17
79 #define EBC_BXAP(n) (0x10+(n))
80 #define EBC_BEAR 0x20
81 #define EBC_BESR 0x21
82 #define EBC_CFG 0x23
83 #define EBC_CID 0x24
86 #define DCRN_CPC0_SR 0x0b0
87 #define DCRN_CPC0_ER 0x0b1
88 #define DCRN_CPC0_FR 0x0b2
89 #define DCRN_CPC0_SYS0 0x0e0
90 #define CPC0_SYS0_TUNE 0xffc00000
91 #define CPC0_SYS0_FBDV_MASK 0x003c0000
92 #define CPC0_SYS0_FWDVA_MASK 0x00038000
93 #define CPC0_SYS0_FWDVB_MASK 0x00007000
94 #define CPC0_SYS0_OPDV_MASK 0x00000c00
95 #define CPC0_SYS0_EPDV_MASK 0x00000300
99 ((((((reg) & CPC0_SYS0_FBDV_MASK) >> 18) - 1) & 0xf) + 1)
108 #define CPC0_SYS0_EXTSL 0x00000080
109 #define CPC0_SYS0_RW_MASK 0x00000060
110 #define CPC0_SYS0_RL 0x00000010
111 #define CPC0_SYS0_ZMIISL_MASK 0x0000000c
112 #define CPC0_SYS0_BYPASS 0x00000002
113 #define CPC0_SYS0_NTO1 0x00000001
114 #define DCRN_CPC0_SYS1 0x0e1
115 #define DCRN_CPC0_CUST0 0x0e2
116 #define DCRN_CPC0_CUST1 0x0e3
117 #define DCRN_CPC0_STRP0 0x0e4
118 #define DCRN_CPC0_STRP1 0x0e5
119 #define DCRN_CPC0_STRP2 0x0e6
120 #define DCRN_CPC0_STRP3 0x0e7
121 #define DCRN_CPC0_GPIO 0x0e8
122 #define DCRN_CPC0_PLB 0x0e9
123 #define DCRN_CPC0_CR1 0x0ea
124 #define DCRN_CPC0_CR0 0x0eb
125 #define CPC0_CR0_SWE 0x80000000
126 #define CPC0_CR0_CETE 0x40000000
127 #define CPC0_CR0_U1FCS 0x20000000
128 #define CPC0_CR0_U0DTE 0x10000000
129 #define CPC0_CR0_U0DRE 0x08000000
130 #define CPC0_CR0_U0DC 0x04000000
131 #define CPC0_CR0_U1DTE 0x02000000
132 #define CPC0_CR0_U1DRE 0x01000000
133 #define CPC0_CR0_U1DC 0x00800000
134 #define CPC0_CR0_U0EC 0x00400000
135 #define CPC0_CR0_U1EC 0x00200000
136 #define CPC0_CR0_UDIV_MASK 0x001f0000
139 #define DCRN_CPC0_MIRQ0 0x0ec
140 #define DCRN_CPC0_MIRQ1 0x0ed
141 #define DCRN_CPC0_JTAGID 0x0ef
143 #define DCRN_MAL0_CFG 0x180
144 #define MAL_RESET 0x80000000
147 #define DCRN_CPR0_ADDR 0xc
148 #define DCRN_CPR0_DATA 0xd
149 #define CPR0_PLLD0 0x60
150 #define CPR0_OPBD0 0xc0
151 #define CPR0_PERD0 0xe0
152 #define CPR0_PRIMBD0 0xa0
153 #define CPR0_SCPID 0x120
154 #define CPR0_PLLC0 0x40
157 #define DCRN_CPR0_CLKUPD 0x020
158 #define DCRN_CPR0_PLLC 0x040
159 #define DCRN_CPR0_PLLD 0x060
160 #define DCRN_CPR0_PRIMAD 0x080
161 #define DCRN_CPR0_PRIMBD 0x0a0
162 #define DCRN_CPR0_OPBD 0x0c0
163 #define DCRN_CPR0_PERD 0x0e0
164 #define DCRN_CPR0_MALD 0x100
166 #define DCRN_SDR0_CONFIG_ADDR 0xe
167 #define DCRN_SDR0_CONFIG_DATA 0xf
177 #define DCRN_SDR0_UART0 0x0120
178 #define DCRN_SDR0_UART1 0x0121
179 #define DCRN_SDR0_UART2 0x0122
180 #define DCRN_SDR0_UART3 0x0123
185 #define DCRN_CPR0_CFGADDR 0xc
186 #define DCRN_CPR0_CFGDATA 0xd