Lines Matching +full:read +full:- +full:1
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 /* low-level asm for "intrigue" (PA8500-8700 CPU perf counters)
5 * Copyright (C) 2001 Randolph Chung <tausq at parisc-linux.org>
6 * Copyright (C) 2001 Hewlett-Packard (Grant Grundler)
91 ;* arg0 : rdr to be read
98 ;* arg0 : rdr to be read
100 ;* %r24 - original DR2 value
101 ;* %r1 - scratch
102 ;* %r29 - scratch
114 ; read(shift in) the RDR.
117 ; NOTE: The PCX-W ERS states that DR2_SLOW_RET must be set before any
121 depdi,z 1,DR2_SLOW_RET,1,%r29
132 ; Cacheline start (32-byte cacheline)
141 blr %r1,%r0 ; branch to 8-instruction sequence
145 ; Cacheline start (32-byte cacheline)
155 MTDIAG_1 (1) ; mtdiag %dr1, %r1
161 ; RDR 1 sequence
165 SFDIAG (1)
173 ; RDR 2 read sequence
179 MTDIAG_1 (1)
185 ; RDR 3 read sequence
197 ; RDR 4 read sequence
209 ; RDR 5 read sequence
221 ; RDR 6 read sequence
233 ; RDR 7 read sequence
245 ; RDR 8 read sequence
257 ; RDR 9 read sequence
269 ; RDR 10 read sequence
275 MTDIAG_1 (1)
281 ; RDR 11 read sequence
287 MTDIAG_1 (1)
293 ; RDR 12 read sequence
305 ; RDR 13 read sequence
317 ; RDR 14 read sequence
323 MTDIAG_1 (1)
329 ; RDR 15 read sequence
341 ; RDR 16 read sequence
353 ; RDR 17 read sequence
359 MTDIAG_1 (1)
365 ; RDR 18 read sequence
371 MTDIAG_1 (1)
377 ; RDR 19 read sequence
389 ; RDR 20 read sequence
401 ; RDR 21 read sequence
413 ; RDR 22 read sequence
425 ; RDR 23 read sequence
437 ; RDR 24 read sequence
449 ; RDR 25 read sequence
461 ; RDR 26 read sequence
467 MTDIAG_1 (1)
473 ; RDR 27 read sequence
479 MTDIAG_1 (1)
485 ; RDR 28 read sequence
497 ; RDR 29 read sequence
509 ; RDR 30 read sequence
515 MTDIAG_1 (1)
521 ; RDR 31 read sequence
549 ;* This routine moves data to the RDR's. The double-word that
556 ;* arg1 = 64-bit value to write
557 ;* %r24 - DR2 | DR2_SLOW_RET
558 ;* %r23 - original DR2 value
572 ; NOTE: The PCX-W ERS states that DR2_SLOW_RET must be set before any
576 depdi,z 1,DR2_SLOW_RET,1,%r24
582 blr %r1,%r0 ; branch to 8-instruction sequence
598 ; RDR 1 write sequence
602 STDIAG (1)
989 ;* arg0 : rdr to be read
996 ;* arg0 : rdr to be read
998 ;* %r24 - original DR2 value
999 ;* %r23 - DR2 | DR2_SLOW_RET
1000 ;* %r1 - scratch
1009 ; read(shift in) the RDR.
1011 ; NOTE: The PCX-U ERS states that DR2_SLOW_RET must be set before any
1014 depdi,z 1,DR2_SLOW_RET,1,%r29
1025 ; Start of next 32-byte cacheline
1034 blr %r1,%r0 ; branch to 8-instruction sequence
1038 ; Start of next 32-byte cacheline
1040 SFDIAG (0) ; RDR 0 read sequence
1044 MTDIAG_1 (1)
1049 SFDIAG (1) ; RDR 1 read sequence
1053 MTDIAG_1 (1)
1054 STDIAG (1)
1058 sync ; RDR 2 read sequence
1067 sync ; RDR 3 read sequence
1076 sync ; RDR 4 read sequence
1085 sync ; RDR 5 read sequence
1094 sync ; RDR 6 read sequence
1103 sync ; RDR 7 read sequence
1121 SFDIAG (9) ; RDR 9 read sequence
1125 MTDIAG_1 (1)
1130 SFDIAG (10) ; RDR 10 read sequence
1134 MTDIAG_1 (1)
1139 SFDIAG (11) ; RDR 11 read sequence
1143 MTDIAG_1 (1)
1148 SFDIAG (12) ; RDR 12 read sequence
1152 MTDIAG_1 (1)
1157 SFDIAG (13) ; RDR 13 read sequence
1161 MTDIAG_1 (1)
1166 SFDIAG (14) ; RDR 14 read sequence
1170 MTDIAG_1 (1)
1175 SFDIAG (15) ; RDR 15 read sequence
1179 MTDIAG_1 (1)
1184 sync ; RDR 16 read sequence
1193 SFDIAG (17) ; RDR 17 read sequence
1197 MTDIAG_1 (1)
1202 SFDIAG (18) ; RDR 18 read sequence
1206 MTDIAG_1 (1)
1220 sync ; RDR 20 read sequence
1229 sync ; RDR 21 read sequence
1238 sync ; RDR 22 read sequence
1247 sync ; RDR 23 read sequence
1256 sync ; RDR 24 read sequence
1265 sync ; RDR 25 read sequence
1274 SFDIAG (26) ; RDR 26 read sequence
1278 MTDIAG_1 (1)
1283 SFDIAG (27) ; RDR 27 read sequence
1287 MTDIAG_1 (1)
1292 sync ; RDR 28 read sequence
1310 SFDIAG (30) ; RDR 30 read sequence
1314 MTDIAG_1 (1)
1319 SFDIAG (31) ; RDR 31 read sequence
1323 MTDIAG_1 (1)
1341 ;* This routine moves data to the RDR's. The double-word that
1356 ;* %r24 - DR2 | DR2_SLOW_RET
1357 ;* %r23 - original DR2 value
1367 ; NOTE: The PCX-U ERS states that DR2_SLOW_RET must be set before any
1371 depdi,z 1,DR2_SLOW_RET,1,%r24
1378 blr %r1,%r0 ; branch to 8-instruction sequence
1382 ; 32-byte cachline aligned
1394 sync ; RDR 1 write sequence
1396 STDIAG (1)