Lines Matching +full:alternative +full:- +full:a
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Copyright (C) 2000-2001 Hewlett-Packard (John Marvin)
5 * Copyright (C) 2001 Matthew Wilcox (willy at parisc-linux.org)
6 * Copyright (C) 2002 Richard Hirst (rhirst with parisc-linux.org)
26 #include <asm/alternative.h>
42 /* pcxt_ssm_bug - relied upon translation! PA 2.0 Arch. F-4 and F-5 */
43 rsm PSW_SM_I, %r19 /* save I-bit state */
74 addib,COND(=) -1, %arg3, fitoneloop /* Preadjust and test */
84 addib,COND(>) -1, %r31, fitmanymiddle /* Adjusted inner loop decr */
87 addib,COND(>) -1, %r29, fitmanymiddle /* Middle loop decr */
88 copy %arg3, %r31 /* Re-init inner loop count */
90 movb,tr %arg0, %r28, fitmanyloop /* Re-init base addr */
91 addib,COND(<=),n -1, %r22, fitdone /* Outer loop count decr */
99 addib,COND(>) -1, %r29, fitonemiddle /* Middle loop count decr */
102 addib,COND(>) -1, %r22, fitoneloop /* Outer loop count decr */
106 ALTERNATIVE(88b, fitdone, ALT_COND_NO_SPLIT_TLB, INSN_NOP)
118 addib,COND(=) -1, %arg3, fdtoneloop /* Preadjust and test */
128 addib,COND(>) -1, %r31, fdtmanymiddle /* Adjusted inner loop decr */
131 addib,COND(>) -1, %r29, fdtmanymiddle /* Middle loop decr */
132 copy %arg3, %r31 /* Re-init inner loop count */
134 movb,tr %arg0, %r28, fdtmanyloop /* Re-init base addr */
135 addib,COND(<=),n -1, %r22,fdtdone /* Outer loop count decr */
143 addib,COND(>) -1, %r29, fdtonemiddle /* Middle loop count decr */
146 addib,COND(>) -1, %r22, fdtoneloop /* Outer loop count decr */
170 or %r1, %r19, %r1 /* I-bit to state on entry */
171 mtctl %r1, %ipsw /* restore I-bit (entire PSW) */
201 addib,COND(=) -1, %arg3, fioneloop /* Preadjust and test */
205 addib,COND(>) -1, %r31, fimanyloop /* Adjusted inner loop decr */
208 movb,tr %arg3, %r31, fimanyloop /* Re-init inner loop count */
209 addib,COND(<=),n -1, %arg2, fisync /* Outer loop decr */
212 /* Some implementations may flush with a single fice instruction */
231 addib,COND(>) -16, %arg2, fioneloop1
238 addib,COND(>) -1, %arg2, fioneloop2 /* Outer loop count decr */
243 mtsm %r22 /* restore I-bit */
244 89: ALTERNATIVE(88b, 89b, ALT_COND_NO_ICACHE, INSN_NOP)
262 addib,COND(=) -1, %arg3, fdoneloop /* Preadjust and test */
266 addib,COND(>) -1, %r31, fdmanyloop /* Adjusted inner loop decr */
269 movb,tr %arg3, %r31, fdmanyloop /* Re-init inner loop count */
270 addib,COND(<=),n -1, %arg2, fdsync /* Outer loop decr */
273 /* Some implementations may flush with a single fdce instruction */
292 addib,COND(>) -16, %arg2, fdoneloop1
299 addib,COND(>) -1, %arg2, fdoneloop2 /* Outer loop count decr */
304 mtsm %r22 /* restore I-bit */
305 89: ALTERNATIVE(88b, 89b, ALT_COND_NO_DCACHE, INSN_NOP)
337 addib,COND(>),n -1, %r1, 1b
343 * Note that until (if) we start saving the full 64-bit register
344 * values on interrupt, we can't use std on a 32 bit kernel.
366 addib,COND(>),n -1, %r1, 1b
428 addib,COND(>),n -1, %r1, 1b
438 * use ldd/std on a 32 bit kernel.
477 addib,COND(>),n -1, %r1, 1b
485 * NOTE: Code in clear_user_page has a hard coded dependency on the
487 * parisc chip designers that there will not ever be a parisc
488 * chip with a larger alias boundary (Never say never :-) ).
493 * "knowing" that if a dtlb miss happens within the temp alias
508 * copy_user_page_asm() performs a page copy using mappings
514 * page needs to be flushed since code can be copied. As a
523 * lobby for such a change.
538 depi_safe 1, 31-TMPALIAS_SIZE_BITS,1, %r29 /* Form aliased virtual address 'from' */
548 ALTERNATIVE(0b, 0b+4, ALT_COND_NO_SMP, INSN_PxTLB)
549 ALTERNATIVE(1b, 1b+4, ALT_COND_NO_SMP, INSN_PxTLB)
604 * non-taken backward branch. Note that .+4 is a backwards branch.
607 addib,COND(>),n -1, %r1, 1b /* bundle 10 */
619 * use ldd/std on a 32 bit kernel.
656 addib,COND(>) -1, %r1,1b
677 ALTERNATIVE(0b, 0b+4, ALT_COND_NO_SMP, INSN_PxTLB)
702 addib,COND(>) -1, %r1, 1b
724 addib,COND(>) -1, %r1, 1b
743 ALTERNATIVE(0b, 0b+4, ALT_COND_NO_SMP, INSN_PxTLB)
750 depdi,z 1, 63-PAGE_SHIFT,1, %r25
752 depwi,z 1, 31-PAGE_SHIFT,1, %r25
775 89: ALTERNATIVE(88b, 89b, ALT_COND_NO_DCACHE, INSN_NOP)
792 ALTERNATIVE(0b, 0b+4, ALT_COND_NO_SMP, INSN_PxTLB)
799 depdi,z 1, 63-PAGE_SHIFT,1, %r25
801 depwi,z 1, 31-PAGE_SHIFT,1, %r25
824 89: ALTERNATIVE(88b, 89b, ALT_COND_NO_DCACHE, INSN_NOP)
837 * have a flat address space, it's not clear which TLB will be
843 ALTERNATIVE(1b, 1b+4, ALT_COND_NO_SPLIT_TLB, INSN_NOP)
847 ALTERNATIVE(0b, 0b+4, ALT_COND_NO_SMP, INSN_PxTLB)
848 ALTERNATIVE(1b, 1b+4, ALT_COND_NO_SMP, INSN_PxTLB)
849 ALTERNATIVE(1b, 1b+4, ALT_COND_NO_SPLIT_TLB, INSN_NOP)
856 depdi,z 1, 63-PAGE_SHIFT,1, %r25
858 depwi,z 1, 31-PAGE_SHIFT,1, %r25
883 89: ALTERNATIVE(88b, 89b, ALT_COND_NO_ICACHE, INSN_NOP)
895 depdi,z 1, 63-PAGE_SHIFT,1, %r25
897 depwi,z 1, 31-PAGE_SHIFT,1, %r25
920 89: ALTERNATIVE(88b, 89b, ALT_COND_NO_DCACHE, INSN_NOP)
932 depdi,z 1, 63-PAGE_SHIFT,1, %r25
934 depwi,z 1, 31-PAGE_SHIFT,1, %r25
957 89: ALTERNATIVE(88b, 89b, ALT_COND_NO_DCACHE, INSN_NOP)
966 ldo -1(%r23), %r21
998 89: ALTERNATIVE(88b, 89b, ALT_COND_NO_DCACHE, INSN_NOP)
1007 ldo -1(%r23), %r21
1040 89: ALTERNATIVE(88b, 89b, ALT_COND_NO_DCACHE, INSN_NOP)
1048 ldo -1(%r23), %r21
1081 89: ALTERNATIVE(88b, 89b, ALT_COND_NO_DCACHE, INSN_NOP)
1089 ldo -1(%r23), %r21
1121 89: ALTERNATIVE(88b, 89b, ALT_COND_NO_ICACHE, INSN_NOP)
1132 depdi,z 1, 63-PAGE_SHIFT,1, %r25
1134 depwi,z 1, 31-PAGE_SHIFT,1, %r25
1158 89: ALTERNATIVE(88b, 89b, ALT_COND_NO_ICACHE, INSN_NOP)
1167 ldo -1(%r23), %r21
1199 89: ALTERNATIVE(88b, 89b, ALT_COND_NO_ICACHE, INSN_NOP)