Lines Matching refs:ori
38 l.ori gpr,gpr,lo(symbol)
265 l.ori r30,r30,(EXCEPTION_SR) ;\
351 l.ori r30,r0,(EXCEPTION_SR) ;\
527 l.ori r3,r0,0x1
585 l.ori r4,r0,0x0
626 l.ori r28,r28,lo(SPR_SR_DME | SPR_SR_IME)
652 l.ori r4,r4,lo(OF_DT_HEADER)
744 l.ori r25,r25,SPR_SR_IEE
749 l.ori r25,r25,0xffff
800 l.ori r28,r28,lo(SPR_SR_DME | SPR_SR_IME)
851 l.ori r30,r0,16
860 l.ori r30,r0,1
878 l.ori r6,r6,SPR_SR_ICE
917 l.ori r30,r0,16
926 l.ori r30,r0,1
940 l.ori r6,r6,SPR_SR_DCE
1012 l.ori r5, r0, 0x1
1018 l.ori r6,r6,~(VPN_MASK) // r6 <- VPN :VPN .xfff - clear up lo(r6) to 0x**** *fff
1020 l.ori r5,r5,lo(DTLB_MR_MASK) // r5 <- ffff:1111.x001 - apply DTLB_MR_MASK
1032 l.ori r3,r3,~(PPN_MASK) // r3 <- PPN :PPN .xfff - clear up lo(r6) to 0x**** *fff
1034 l.ori r5,r5,lo(DTLB_TR_MASK) // r5 <- ffff:1111.x330 - apply DTLB_MR_MASK
1099 l.ori r5, r0, 0x1
1105 l.ori r6,r6,~(VPN_MASK) // r6 <- VPN :VPN .xfff - clear up lo(r6) to 0x**** *fff
1107 l.ori r5,r5,lo(ITLB_MR_MASK) // r5 <- ffff:1111.x001 - apply ITLB_MR_MASK
1125 l.ori r3,r3,~(PPN_MASK) // r3 <- PPN :PPN .xfff - clear up lo(r6) to 0x**** *fff
1127 l.ori r5,r5,lo(ITLB_TR_MASK) // r5 <- ffff:1111.x050 - apply ITLB_MR_MASK
1212 l.ori r3, r0, 0x1
1224 l.ori r4,r3,0x1 // set hardware valid bit: DTBL_MR entry
1297 l.ori r3, r0, 0x1
1312 l.ori r4,r4,0xc0 // | (SPR_ITLBTR_UXE | ITLBTR_SXE)
1319 l.ori r4,r3,0x1 // set hardware valid bit: ITBL_MR entry
1358 l.ori r4,r4,lo(UART_BASE_ADD)
1511 l.ori r3,r3,lo(UART_BASE_ADD)
1524 l.ori r4,r5,0x80
1542 l.ori r3,r0,SPR_SR_SM