Lines Matching +full:0 +full:x1b00
34 l.movhi gpr,0x0
41 #define UART_BASE_ADD 0x90000000
73 #define EMERGENCY_PRINT_STORE_GPR4 l.sw 0x20(r0),r4
74 #define EMERGENCY_PRINT_LOAD_GPR4 l.lwz r4,0x20(r0)
76 #define EMERGENCY_PRINT_STORE_GPR5 l.sw 0x24(r0),r5
77 #define EMERGENCY_PRINT_LOAD_GPR5 l.lwz r5,0x24(r0)
79 #define EMERGENCY_PRINT_STORE_GPR6 l.sw 0x28(r0),r6
80 #define EMERGENCY_PRINT_LOAD_GPR6 l.lwz r6,0x28(r0)
82 #define EMERGENCY_PRINT_STORE_GPR7 l.sw 0x2c(r0),r7
83 #define EMERGENCY_PRINT_LOAD_GPR7 l.lwz r7,0x2c(r0)
85 #define EMERGENCY_PRINT_STORE_GPR8 l.sw 0x30(r0),r8
86 #define EMERGENCY_PRINT_LOAD_GPR8 l.lwz r8,0x30(r0)
88 #define EMERGENCY_PRINT_STORE_GPR9 l.sw 0x34(r0),r9
89 #define EMERGENCY_PRINT_LOAD_GPR9 l.lwz r9,0x34(r0)
113 #define EXCEPTION_STORE_GPR2 l.sw 0x64(r0),r2
114 #define EXCEPTION_LOAD_GPR2 l.lwz r2,0x64(r0)
116 #define EXCEPTION_STORE_GPR3 l.sw 0x68(r0),r3
117 #define EXCEPTION_LOAD_GPR3 l.lwz r3,0x68(r0)
119 #define EXCEPTION_STORE_GPR4 l.sw 0x6c(r0),r4
120 #define EXCEPTION_LOAD_GPR4 l.lwz r4,0x6c(r0)
122 #define EXCEPTION_STORE_GPR5 l.sw 0x70(r0),r5
123 #define EXCEPTION_LOAD_GPR5 l.lwz r5,0x70(r0)
125 #define EXCEPTION_STORE_GPR6 l.sw 0x74(r0),r6
126 #define EXCEPTION_LOAD_GPR6 l.lwz r6,0x74(r0)
145 #define EXCEPTION_T_STORE_GPR30 l.sw 0x78(r0),r30
146 #define EXCEPTION_T_LOAD_GPR30(reg) l.lwz reg,0x78(r0)
148 #define EXCEPTION_T_STORE_GPR10 l.sw 0x7c(r0),r10
149 #define EXCEPTION_T_LOAD_GPR10(reg) l.lwz reg,0x7c(r0)
151 #define EXCEPTION_T_STORE_SP l.sw 0x80(r0),r1
152 #define EXCEPTION_T_LOAD_SP(reg) l.lwz reg,0x80(r0)
164 l.lwz reg,0(t1)
169 l.lwz reg,0(t1)
181 l.lwz r10,0(r30)
187 l.lwz r10,0(r30)
208 * r12 - syscall 0, since we didn't come from syscall
225 l.sfeqi r30,0 ;\
278 * l.ori r3,r0,0x1 ;\
280 * l.movhi r3,hi(0xf0000100) ;\
281 * l.ori r3,r3,lo(0xf0000100) ;\
298 l.addi r1,r3,0x0 ;\
299 l.addi r10,r9,0x0 ;\
306 l.andi r3,r3,0x1f00 ;\
318 l.addi r3,r1,0x0 ;\
319 l.addi r9,r10,0x0 ;\
362 /* ---[ 0x100: RESET exception ]----------------------------------------- */
363 .org 0x100
372 /* ---[ 0x200: BUS exception ]------------------------------------------- */
373 .org 0x200
377 /* ---[ 0x300: Data Page Fault exception ]------------------------------- */
378 .org 0x300
382 // DEBUG_TLB_PROBE(0x300)
383 // EXCEPTION_DEBUG_VALUE_ER_ENABLED(0x300)
386 /* ---[ 0x400: Insn Page Fault exception ]------------------------------- */
387 .org 0x400
391 // DEBUG_TLB_PROBE(0x400)
392 // EXCEPTION_DEBUG_VALUE_ER_ENABLED(0x400)
395 /* ---[ 0x500: Timer exception ]----------------------------------------- */
396 .org 0x500
399 /* ---[ 0x600: Alignment exception ]------------------------------------- */
400 .org 0x600
403 /* ---[ 0x700: Illegal insn exception ]---------------------------------- */
404 .org 0x700
407 /* ---[ 0x800: External interrupt exception ]---------------------------- */
408 .org 0x800
411 /* ---[ 0x900: DTLB miss exception ]------------------------------------- */
412 .org 0x900
416 /* ---[ 0xa00: ITLB miss exception ]------------------------------------- */
417 .org 0xa00
421 /* ---[ 0xb00: Range exception ]----------------------------------------- */
422 .org 0xb00
425 /* ---[ 0xc00: Syscall exception ]--------------------------------------- */
426 .org 0xc00
429 /* ---[ 0xd00: Floating point exception ]-------------------------------- */
430 .org 0xd00
433 /* ---[ 0xe00: Trap exception ]------------------------------------------ */
434 .org 0xe00
438 /* ---[ 0xf00: Reserved exception ]-------------------------------------- */
439 .org 0xf00
442 /* ---[ 0x1000: Reserved exception ]------------------------------------- */
443 .org 0x1000
446 /* ---[ 0x1100: Reserved exception ]------------------------------------- */
447 .org 0x1100
450 /* ---[ 0x1200: Reserved exception ]------------------------------------- */
451 .org 0x1200
454 /* ---[ 0x1300: Reserved exception ]------------------------------------- */
455 .org 0x1300
458 /* ---[ 0x1400: Reserved exception ]------------------------------------- */
459 .org 0x1400
462 /* ---[ 0x1500: Reserved exception ]------------------------------------- */
463 .org 0x1500
466 /* ---[ 0x1600: Reserved exception ]------------------------------------- */
467 .org 0x1600
470 /* ---[ 0x1700: Reserved exception ]------------------------------------- */
471 .org 0x1700
474 /* ---[ 0x1800: Reserved exception ]------------------------------------- */
475 .org 0x1800
478 /* ---[ 0x1900: Reserved exception ]------------------------------------- */
479 .org 0x1900
482 /* ---[ 0x1a00: Reserved exception ]------------------------------------- */
483 .org 0x1a00
486 /* ---[ 0x1b00: Reserved exception ]------------------------------------- */
487 .org 0x1b00
490 /* ---[ 0x1c00: Reserved exception ]------------------------------------- */
491 .org 0x1c00
494 /* ---[ 0x1d00: Reserved exception ]------------------------------------- */
495 .org 0x1d00
498 /* ---[ 0x1e00: Reserved exception ]------------------------------------- */
499 .org 0x1e00
502 /* ---[ 0x1f00: Reserved exception ]------------------------------------- */
503 .org 0x1f00
506 .org 0x2000
527 l.ori r3,r0,0x1
585 l.ori r4,r0,0x0
600 l.sw (0)(r28),r0
622 * SR[5] = 0, SR[6] = 0, 6th and 7th bit of SR set to 0
650 l.lwz r3,0(r25) /* load magic from fdt into r3 */
711 LOAD_SYMBOL_2_GPR(r5,SPR_DTLBMR_BASE(0))
712 LOAD_SYMBOL_2_GPR(r6,SPR_ITLBMR_BASE(0))
715 l.mtspr r5,r0,0x0
716 l.mtspr r6,r0,0x0
749 l.ori r25,r25,0xffff
769 l.lwz r3,0(r4)
781 l.lwz r10,0(r30)
826 .align 0x2000
844 If BS=0, 16;
864 l.addi r6,r0,0
910 If BS=0, 16;
930 l.addi r6,r0,0
948 #define DTLB_UP_CONVERT_MASK 0x3fa
949 #define ITLB_UP_CONVERT_MASK 0x3a
955 #define DTLB_SMP_CONVERT_MASK 0x3fb
956 #define ITLB_SMP_CONVERT_MASK 0x3b
962 /* mask for DTLB_MR register: - (0) sets V (valid) bit,
965 #define DTLB_MR_MASK 0xfffff001
974 #define DTLB_TR_MASK 0xfffff332
978 #define VPN_MASK 0xfffff000
979 #define PPN_MASK 0xfffff000
984 #if 0
987 l.sfeqi r6,0 // r6 == 0x1 --> SM
1007 …l.srli r3,r4,0xd // r3 <- r4 / 8192 (sets are relative to page size (8Kb) NOT VPN…
1012 l.ori r5, r0, 0x1
1018 l.ori r6,r6,~(VPN_MASK) // r6 <- VPN :VPN .xfff - clear up lo(r6) to 0x**** *fff
1022 l.mtspr r2,r5,SPR_DTLBMR_BASE(0) // set DTLBMR
1024 /* set up DTLB with no translation for EA <= 0xbfffffff */
1025 LOAD_SYMBOL_2_GPR(r6,0xbfffffff)
1026 l.sfgeu r6,r4 // flag if r6 >= r4 (if 0xbfffffff >= EA)
1032 l.ori r3,r3,~(PPN_MASK) // r3 <- PPN :PPN .xfff - clear up lo(r6) to 0x**** *fff
1036 l.mtspr r2,r5,SPR_DTLBTR_BASE(0) // set DTLBTR
1059 #define ITLB_MR_MASK 0xfffff001
1065 #define ITLB_TR_MASK 0xfffff050
1068 #define VPN_MASK 0xffffe000
1069 #define PPN_MASK 0xffffe000
1080 #if 0
1083 l.sfeqi r6,0 // r6 == 0x1 --> SM
1094 …l.srli r3,r4,0xd // r3 <- r4 / 8192 (sets are relative to page size (8Kb) NOT VP…
1099 l.ori r5, r0, 0x1
1105 l.ori r6,r6,~(VPN_MASK) // r6 <- VPN :VPN .xfff - clear up lo(r6) to 0x**** *fff
1109 l.mtspr r2,r5,SPR_ITLBMR_BASE(0) // set ITLBMR
1112 * set up ITLB with no translation for EA <= 0x0fffffff
1118 LOAD_SYMBOL_2_GPR(r6,0x0fffffff)
1119 l.sfgeu r6,r4 // flag if r6 >= r4 (if 0xb0ffffff >= EA)
1125 l.ori r3,r3,~(PPN_MASK) // r3 <- PPN :PPN .xfff - clear up lo(r6) to 0x**** *fff
1129 l.mtspr r2,r5,SPR_ITLBTR_BASE(0) // set ITLBTR
1173 l.srli r4,r2,0x18 // >> PAGE_SHIFT + (PAGE_SHIFT - 2)
1174 l.slli r4,r4,0x2 // to get address << 2
1181 l.lwz r3,0x0(r4) // get *pmd value
1184 l.addi r3,r0,0xffffe000 // PAGE_MASK
1190 l.lwz r4,0x0(r4) // get **pmd value
1192 l.srli r2,r2,0xd // >> PAGE_SHIFT, r2 == EEAR
1193 l.andi r3,r2,0x7ff // (1UL << PAGE_SHIFT - 2) - 1
1194 l.slli r3,r3,0x2 // to get address << 2
1196 l.lwz r3,0x0(r3) // this is pte at last
1200 l.andi r4,r3,0x1
1203 l.addi r4,r0,0xffffe3fa // PAGE_MASK | DTLB_UP_CONVERT_MASK
1212 l.ori r3, r0, 0x1
1216 l.srli r3, r3, 0xd // >> PAGE_SHIFT
1219 l.mtspr r2,r4,SPR_DTLBTR_BASE(0)
1223 l.slli r3, r3, 0xd /* << PAGE_SHIFT => EA & PAGE_MASK */
1224 l.ori r4,r3,0x1 // set hardware valid bit: DTBL_MR entry
1225 l.mtspr r2,r4,SPR_DTLBMR_BASE(0)
1253 l.srli r4,r2,0x18 // >> PAGE_SHIFT + (PAGE_SHIFT - 2)
1254 l.slli r4,r4,0x2 // to get address << 2
1261 l.lwz r3,0x0(r4) // get *pmd value
1264 l.addi r3,r0,0xffffe000 // PAGE_MASK
1271 l.lwz r4,0x0(r4) // get **pmd value
1273 l.srli r2,r2,0xd // >> PAGE_SHIFT, r2 == EEAR
1274 l.andi r3,r2,0x7ff // (1UL << PAGE_SHIFT - 2) - 1
1275 l.slli r3,r3,0x2 // to get address << 2
1277 l.lwz r3,0x0(r3) // this is pte at last
1282 l.andi r4,r3,0x1
1285 l.addi r4,r0,0xffffe03a // PAGE_MASK | ITLB_UP_CONVERT_MASK
1290 l.andi r3,r3,0x7c0 // _PAGE_EXEC | _PAGE_SRE | _PAGE_SWE | _PAGE_URE | _PAGE_UWE
1297 l.ori r3, r0, 0x1
1301 l.srli r3, r3, 0xd // >> PAGE_SHIFT
1312 l.ori r4,r4,0xc0 // | (SPR_ITLBTR_UXE | ITLBTR_SXE)
1314 l.mtspr r2,r4,SPR_ITLBTR_BASE(0)
1318 l.slli r3, r3, 0xd /* << PAGE_SHIFT => EA & PAGE_MASK */
1319 l.ori r4,r3,0x1 // set hardware valid bit: ITBL_MR entry
1320 l.mtspr r2,r4,SPR_ITLBMR_BASE(0)
1363 l.andi r5,r5,0xff
1364 l.sfnei r5,0
1369 l.andi r7,r7,0xff
1370 l.sw 0(r4),r7
1373 l.addi r6,r0,0x20
1375 l.andi r5,r5,0x20
1381 l.sb 0(r4),r7
1384 l.addi r6,r0,0x60
1386 l.andi r5,r5,0x60
1412 2: l.lbz r7,0(r3)
1413 l.sfeqi r7,0x0
1422 l.addi r3,r3,0x1
1447 l.addi r8,r8,-0x4
1449 l.andi r7,r7,0xf
1451 /* don't skip the last zero if number == 0x0 */
1452 l.sfeqi r8,0x4
1463 l.andi r7,r7,0xf
1468 l.sfgtui r7,0x9
1471 l.addi r7,r7,0x27
1475 l.addi r7,r7,0x30
1479 l.addi r8,r8,-0x4
1514 l.addi r4,r0,0x7
1515 l.sb 0x2(r3),r4
1517 l.addi r4,r0,0x0
1518 l.sb 0x1(r3),r4
1520 l.addi r4,r0,0x3
1521 l.sb 0x3(r3),r4
1524 l.ori r4,r5,0x80
1525 l.sb 0x3(r3),r4
1526 l.addi r4,r0,((UART_DIVISOR>>8) & 0x000000ff)
1528 l.addi r4,r0,((UART_DIVISOR) & 0x000000ff)
1530 l.sb 0x3(r3),r5
1536 .align 0x1000
1540 .space 0x800
1549 .string "\r\nRunarunaround: Unhandled exception 0x\0"
1552 .string ": EPC=0x\0"
1555 .string "\r\n\0"