Lines Matching +full:0 +full:x1900
48 l.addi r2,r1,0 /* move sp to fp */ ;\
51 l.ori r1,r2,0 /* restore sp */ ;\
62 l.addi r2,r1,0 /* move sp to fp */ ;\
65 l.ori r1,r2,0 /* restore sp */ ;\
218 l.addi r3,r1,0 ;\
230 l.sw 0(reg),r0
244 /* ---[ 0x100: RESET exception ]----------------------------------------- */
248 l.andi r0,r0,0
250 /* ---[ 0x200: BUS exception ]------------------------------------------- */
256 l.addi r3,r1,0 /* pt_regs */
261 /* ---[ 0x300: Data Page Fault exception ]------------------------------- */
271 l.ori r5,r0,0x300 // exception vector
273 l.addi r3,r1,0 // pt_regs
278 l.lwz r6,0(r6) // instruction that caused pf
281 l.sfeqi r6,0 // l.j
289 l.sfeqi r6,0x11 // l.jr
291 l.sfeqi r6,0x12 // l.jalr
301 l.lwz r6,0(r6) // instruction that caused pf
315 l.lwz r6,0(r6) // instruction that caused pf
319 l.sfgeui r6,0x33 // check opcode for write access
321 l.sfleui r6,0x37
323 l.ori r6,r0,0x1 // write access
326 1: l.ori r6,r0,0x0 // !write access
335 /* ---[ 0x400: Insn Page Fault exception ]------------------------------- */
345 l.ori r5,r0,0x400 // exception vector
347 l.addi r3,r1,0 // pt_regs
349 l.ori r6,r0,0x0 // !write access
358 /* ---[ 0x500: Timer exception ]----------------------------------------- */
363 l.addi r3,r1,0 /* pt_regs */
368 /* ---[ 0x600: Alignment exception ]-------------------------------------- */
374 l.addi r3,r1,0 /* pt_regs */
379 #if 0
382 l.addi r2,r4,0
386 l.lwz r3,0(r5) /* Load insn */
389 l.sfeqi r4,0x00 /* Check if the load/store insn is in delay slot */
391 l.sfeqi r4,0x01
393 l.sfeqi r4,0x03
395 l.sfeqi r4,0x04
397 l.sfeqi r4,0x11
399 l.sfeqi r4,0x12
418 l.andi r4,r4,0x7c
423 l.lwz r5,0(r4)
432 l.sfeqi r4,0x26
434 l.sfeqi r4,0x25
436 l.sfeqi r4,0x22
438 l.sfeqi r4,0x21
440 l.sfeqi r4,0x37
442 l.sfeqi r4,0x35
449 lhs: l.lbs r5,0(r2)
454 l.andi r4,r4,0x7c
457 l.sw 0(r4),r5
459 lhz: l.lbz r5,0(r2)
464 l.andi r4,r4,0x7c
467 l.sw 0(r4),r5
469 lws: l.lbs r5,0(r2)
480 l.andi r4,r4,0x7c
483 l.sw 0(r4),r5
485 lwz: l.lbz r5,0(r2)
496 l.andi r4,r4,0x7c
499 l.sw 0(r4),r5
503 l.andi r4,r4,0x7c
505 l.lwz r5,0(r4)
509 l.sb 0(r2),r5
513 l.andi r4,r4,0x7c
515 l.lwz r5,0(r4)
523 l.sb 0(r2),r5
530 /* ---[ 0x700: Illegal insn exception ]---------------------------------- */
535 l.addi r3,r1,0 /* pt_regs */
540 /* ---[ 0x800: External interrupt exception ]---------------------------- */
546 l.sfeqi r4,0
551 l.addi r1,r1,-0x8
554 l.sw 0x0(r1),r3
556 l.sw 0x4(r1),r4
557 l.addi r1,r1,0x8
571 l.addi r3,r1,0
579 /* ---[ 0x900: DTLB miss exception ]------------------------------------- */
582 /* ---[ 0xa00: ITLB miss exception ]------------------------------------- */
585 /* ---[ 0xb00: Range exception ]----------------------------------------- */
587 UNHANDLED_EXCEPTION(_vector_0xb00,0xb00)
589 /* ---[ 0xc00: Syscall exception ]--------------------------------------- */
604 .string "syscall r9:0x%08x -> syscall(%ld) return %ld\0"
667 l.lwz r29,0(r29)
678 #if 0
695 #if 0
719 l.ori r3,r1,0
817 l.addi r3,r1,0
835 l.addi r3,r1,0
851 /* ---[ 0xd00: Floating Point exception ]-------------------------------- */
858 l.addi r3,r1,0 /* pt_regs */
863 /* ---[ 0xe00: Trap exception ]------------------------------------------ */
869 l.addi r3,r1,0 /* pt_regs */
874 /* ---[ 0xf00: Reserved exception ]-------------------------------------- */
876 UNHANDLED_EXCEPTION(_vector_0xf00,0xf00)
878 /* ---[ 0x1000: Reserved exception ]------------------------------------- */
880 UNHANDLED_EXCEPTION(_vector_0x1000,0x1000)
882 /* ---[ 0x1100: Reserved exception ]------------------------------------- */
884 UNHANDLED_EXCEPTION(_vector_0x1100,0x1100)
886 /* ---[ 0x1200: Reserved exception ]------------------------------------- */
888 UNHANDLED_EXCEPTION(_vector_0x1200,0x1200)
890 /* ---[ 0x1300: Reserved exception ]------------------------------------- */
892 UNHANDLED_EXCEPTION(_vector_0x1300,0x1300)
894 /* ---[ 0x1400: Reserved exception ]------------------------------------- */
896 UNHANDLED_EXCEPTION(_vector_0x1400,0x1400)
898 /* ---[ 0x1500: Reserved exception ]------------------------------------- */
900 UNHANDLED_EXCEPTION(_vector_0x1500,0x1500)
902 /* ---[ 0x1600: Reserved exception ]------------------------------------- */
904 UNHANDLED_EXCEPTION(_vector_0x1600,0x1600)
906 /* ---[ 0x1700: Reserved exception ]------------------------------------- */
908 UNHANDLED_EXCEPTION(_vector_0x1700,0x1700)
910 /* ---[ 0x1800: Reserved exception ]------------------------------------- */
912 UNHANDLED_EXCEPTION(_vector_0x1800,0x1800)
914 /* ---[ 0x1900: Reserved exception ]------------------------------------- */
916 UNHANDLED_EXCEPTION(_vector_0x1900,0x1900)
918 /* ---[ 0x1a00: Reserved exception ]------------------------------------- */
920 UNHANDLED_EXCEPTION(_vector_0x1a00,0x1a00)
922 /* ---[ 0x1b00: Reserved exception ]------------------------------------- */
924 UNHANDLED_EXCEPTION(_vector_0x1b00,0x1b00)
926 /* ---[ 0x1c00: Reserved exception ]------------------------------------- */
928 UNHANDLED_EXCEPTION(_vector_0x1c00,0x1c00)
930 /* ---[ 0x1d00: Reserved exception ]------------------------------------- */
932 UNHANDLED_EXCEPTION(_vector_0x1d00,0x1d00)
934 /* ---[ 0x1e00: Reserved exception ]------------------------------------- */
936 UNHANDLED_EXCEPTION(_vector_0x1e00,0x1e00)
938 /* ---[ 0x1f00: Reserved exception ]------------------------------------- */
940 UNHANDLED_EXCEPTION(_vector_0x1f00,0x1f00)
949 l.sfeqi r13,0
955 l.sfltsi r5,0
958 l.andi r5,r5,0
961 l.ori r3,r1,0 /* pt_regs */
963 l.sfeqi r11,0
966 l.sfltsi r11,0
1002 l.sfeqi r3,0
1013 l.sfeqi r20,0
1081 .align 0x400
1104 l.addi r11,r10,0 /* Save old 'current' to 'last' return value*/
1202 l.addi r3,r1,0
1207 l.addi r3,r1,0
1229 l.lwz r29,0(r4)
1230 l.lwz r27,0(r5)
1231 l.sw 0(r4),r27
1232 l.sw 0(r5),r29