1 // SPDX-License-Identifier: GPL-2.0-only
6  * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
18 #include <asm/mach-ralink/ralink_regs.h>
19 #include <asm/mach-ralink/mt7620.h>
45 /* does the board have sdram or ddram */
55 		pr_info("Board has SDRAM\n");  in mt7620_dram_init()
56 		soc_info->mem_size_min = MT7620_SDRAM_SIZE_MIN;  in mt7620_dram_init()
57 		soc_info->mem_size_max = MT7620_SDRAM_SIZE_MAX;  in mt7620_dram_init()
61 		pr_info("Board has DDR1\n");  in mt7620_dram_init()
62 		soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN;  in mt7620_dram_init()
63 		soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX;  in mt7620_dram_init()
67 		pr_info("Board has DDR2\n");  in mt7620_dram_init()
68 		soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN;  in mt7620_dram_init()
69 		soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX;  in mt7620_dram_init()
81 		pr_info("Board has DDR1\n");  in mt7628_dram_init()
82 		soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN;  in mt7628_dram_init()
83 		soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX;  in mt7628_dram_init()
87 		pr_info("Board has DDR2\n");  in mt7628_dram_init()
88 		soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN;  in mt7628_dram_init()
89 		soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX;  in mt7628_dram_init()
156 			soc_info->compatible = "ralink,mt7620a-soc";  in mt7620_get_soc_name()
160 			soc_info->compatible = "ralink,mt7620n-soc";  in mt7620_get_soc_name()
174 		soc_info->compatible = "ralink,mt7628an-soc";  in mt7620_get_soc_name()
203 		return -ENOMEM;  in mt7620_soc_dev_init()
205 	soc_dev_attr->family = "Ralink";  in mt7620_soc_dev_init()
206 	soc_dev_attr->soc_id = mt7620_get_soc_id_name();  in mt7620_soc_dev_init()
208 	soc_dev_attr->data = soc_info_ptr;  in mt7620_soc_dev_init()
227 	snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,  in prom_soc_init()
241 	soc_info->mem_base = MT7620_DRAM_BASE;  in prom_soc_init()
250 	pr_info("Analog PMU set to %s control\n",  in prom_soc_init()
252 	pr_info("Digital PMU set to %s control\n",  in prom_soc_init()