6  * Copyright (C) 2005-2009 Cavium Networks
20 #include <asm/octeon/cvmx-npi-defs.h>
21 #include <asm/octeon/cvmx-pci-defs.h>
22 #include <asm/octeon/pci-octeon.h>
108 	if (dev->subordinate) {  in pcibios_plat_dev_init()
119 	config |= PCI_EXP_DEVCTL_NFERE; /* Non-Fatal Error Reporting */  in pcibios_plat_dev_init()
133 		/* Uncorrectable Error Mask - turned on bits disable errors */  in pcibios_plat_dev_init()
140 		/* PCI_ERR_UNCOR_SEVER - Uncorrectable Error Severity */  in pcibios_plat_dev_init()
145 		/* Correctable Error Mask - turned on bits disable errors */  in pcibios_plat_dev_init()
156 		/* PCI_ERR_HEADER_LOG - Header Log Register (16 bytes) */  in pcibios_plat_dev_init()
174  * first character, etc. The characters A-D are used for PCI
202 	if (of_machine_is_compatible("dlink,dsr-500n"))  in octeon_get_pci_interrupts()
204 	switch (octeon_bootinfo->board_type) {  in octeon_get_pci_interrupts()
244 	dev_num = dev->devfn >> 3;  in octeon_pci_pcibios_map_irq()
246 		irq_num = ((interrupts[dev_num] - 'A' + pin - 1) & 3) +  in octeon_pci_pcibios_map_irq()
249 		irq_num = ((slot + pin - 3) & 3) + OCTEON_IRQ_PCI_INT0;  in octeon_pci_pcibios_map_irq()
268 	pci_addr.s.bus = bus->number;  in octeon_read_config()
302 	pci_addr.s.bus = bus->number;  in octeon_write_config()
335  * PCI ports must be above 16KB so the ISA bus filtering in the PCI-X to PCI
340 	.end = OCTEON_PCI_IOSPACE_SIZE - 1,
408 	pr_notice("PCI Status: %s %s-bit\n",  in octeon_pci_initialize()
409 		  ctl_status_2.s.ap_pcix ? "PCI-X" : "PCI",  in octeon_pci_initialize()
421 		cycles = read_c0_cvmcount() - cycles;  in octeon_pci_initialize()
422 		pci_clock = (cnt_reg_end.s.pcicnt - cnt_reg_start.s.pcicnt) /  in octeon_pci_initialize()
429 	 * in PCI-X mode to allow four outstanding splits. Otherwise,  in octeon_pci_initialize()
432 	 * after PCI-X mode is known. MRBCI,MDWE,MDRE -> must be zero.  in octeon_pci_initialize()
433 	 * MRBCM -> must be one.  in octeon_pci_initialize()
457 		 * 2 SAC cycles. NOTE: For the PCI-X maximum  in octeon_pci_initialize()
490 	 * internal arbiter, so must enable it before any PCI/PCI-X  in octeon_pci_initialize()
504 	 * TWTAE,TMAE,DPPMR -> must be zero. TILT -> must not be set to  in octeon_pci_initialize()
512 	 * Should be written to 0x4ff00. MTTV -> must be zero.  in octeon_pci_initialize()
513 	 * FLUSH -> must be 1. MRV -> should be 0xFF.  in octeon_pci_initialize()
526 	 * MOST Indicates the maximum number of outstanding splits (in -1  in octeon_pci_initialize()
527 	 * notation) when OCTEON is in PCI-X mode.  PCI-X performance is  in octeon_pci_initialize()
533 	cfg56.s.pxcid = 7;	/* RO - PCI-X Capability ID */  in octeon_pci_initialize()
534 	cfg56.s.ncp = 0xe8;	/* RO - Next Capability Pointer */  in octeon_pci_initialize()
548 	 * PCI_READ_CMD_E, respectively. Unfortunately due to errata DDR-700,  in octeon_pci_initialize()
590 	ioport_resource.end = OCTEON_PCI_IOSPACE_SIZE - 1;  in octeon_pci_setup()
599 	mem_access.s.esr = 1;	/* Endian-Swap on read. */  in octeon_pci_setup()
600 	mem_access.s.esw = 1;	/* Endian-Swap on write. */  in octeon_pci_setup()
601 	mem_access.s.nsr = 0;	/* No-Snoop on read. */  in octeon_pci_setup()
602 	mem_access.s.nsw = 0;	/* No-Snoop on write. */  in octeon_pci_setup()
620 		/* Remap the Octeon BAR 0 to 0-2GB */  in octeon_pci_setup()
625 		 * Remap the Octeon BAR 1 to map 2GB-4GB (minus the  in octeon_pci_setup()
652 			OCTEON_PCI_MEMSPACE_OFFSET + (4ul << 30) -  in octeon_pci_setup()
657 		/* Remap the Octeon BAR 0 to map 128MB-(128MB+4KB) */  in octeon_pci_setup()
661 		/* Remap the Octeon BAR 1 to map 0-128MB */  in octeon_pci_setup()
667 			default_swiotlb_base() & ~((1ull << 22) - 1);  in octeon_pci_setup()
700 	cvmx_write_csr(CVMX_NPI_PCI_INT_SUM2, -1);  in octeon_pci_setup()
703 						   -1, NULL, 0)))  in octeon_pci_setup()