Lines Matching +full:bus +full:- +full:range

1 // SPDX-License-Identifier: GPL-2.0-or-later
4  * Copyright (C) 2003, 04, 11 Ralf Baechle (ralf@linux-mips.org)
6  *   written by Ralf Baechle (ralf@linux-mips.org)
18 #include <asm/cpu-info.h>
35 		return (unsigned long)-1;
43  * addresses to be allocated in the 0x000-0x0ff region
47  * the low 10 bits of the IO address. The 0x00-0xff region
49  * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
50  * but we want to try to avoid allocating at 0x2900-0x2bff
51  * which might have be mirrored at 0x0100-0x03ff..
58 	struct pci_controller *hose = dev->sysdata;
59 	resource_size_t start = res->start;
61 	if (res->flags & IORESOURCE_IO) {
63 		if (start < PCIBIOS_MIN_IO + hose->io_resource->start)
64 			start = PCIBIOS_MIN_IO + hose->io_resource->start;
67 		 * Put everything into 0x00-0xff region modulo 0x400
71 	} else if (res->flags & IORESOURCE_MEM) {
73 		if (start < PCIBIOS_MIN_MEM + hose->mem_resource->start)
74 			start = PCIBIOS_MIN_MEM + hose->mem_resource->start;
85 	struct pci_bus *bus;
93 	if (hose->get_busno && pci_has_flag(PCI_PROBE_ONLY))
94 		next_busno = (*hose->get_busno)();
97 				hose->mem_resource, hose->mem_offset);
99 				hose->io_resource, hose->io_offset);
100 	list_splice_init(&resources, &bridge->windows);
101 	bridge->dev.parent = NULL;
102 	bridge->sysdata = hose;
103 	bridge->busnr = next_busno;
104 	bridge->ops = hose->pci_ops;
105 	bridge->swizzle_irq = pci_common_swizzle;
106 	bridge->map_irq = pcibios_map_irq;
113 	hose->bus = bus = bridge->bus;
115 	need_domain_info = need_domain_info || pci_domain_nr(bus);
118 	next_busno = bus->busn_res.end + 1;
119 	/* Don't allow 8-bit bus number overflow inside the hose -
132 		pci_bus_claim_resources(bus);
136 		pci_bus_size_bridges(bus);
137 		pci_bus_assign_resources(bus);
138 		list_for_each_entry(child, &bus->children, node)
141 	pci_bus_add_devices(bus);
147 	struct of_pci_range range;
150 	hose->of_node = node;
155 	for_each_of_pci_range(&parser, &range) {
158 		switch (range.flags & IORESOURCE_TYPE_BITS) {
160 			hose->io_map_base =
161 				(unsigned long)ioremap(range.cpu_addr,
162 						       range.size);
163 			res = hose->io_resource;
166 			res = hose->mem_resource;
170 			res->name = node->full_name;
171 			res->flags = range.flags;
172 			res->start = range.cpu_addr;
173 			res->end = range.cpu_addr + range.size - 1;
174 			res->parent = res->child = res->sibling = NULL;
179 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
181 	struct pci_controller *hose = bus->sysdata;
183 	return of_node_get(hose->of_node);
193 	parent = hose->mem_resource->parent;
197 	if (request_resource(parent, hose->mem_resource) < 0)
200 	parent = hose->io_resource->parent;
204 	if (request_resource(parent, hose->io_resource) < 0) {
205 		release_resource(hose->mem_resource);
209 	INIT_LIST_HEAD(&hose->list);
210 	list_add_tail(&hose->list, &controllers);
213 	 * Do not panic here but later - this might happen before console init.
215 	if (!hose->io_map_base) {
221 	 * Scan the bus if it is register after the PCI subsystem
234 	       "Skipping PCI bus scan due to resource conflict\n");
265 		if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
268 				(!(r->flags & IORESOURCE_ROM_ENABLE)))
270 		if (!r->start && r->end) {
273 			return -EINVAL;
275 		if (r->flags & IORESOURCE_IO)
277 		if (r->flags & IORESOURCE_MEM)
281 		pci_info(dev, "enabling device (%04x -> %04x)\n", old_cmd, cmd);
297 void pcibios_fixup_bus(struct pci_bus *bus)
299 	struct pci_dev *dev = bus->self;
302 	    (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
303 		pci_read_bridge_bases(bus);