6  * A small micro-assembler. It is intentionally kept simple, does only
12  * Copyright (C) 2006  Ralf Baechle (ralf@linux-mips.org)
31 /* This macro sets the non-variable bits of an instruction. */
40 /* This macro sets the non-variable bits of an R6 instruction. */
73 	[insn_cfcmsa]	= {M(msa_op, 0, msa_cfc_op, 0, 0, msa_elm_op), RD | RE},
75 	[insn_ctcmsa]	= {M(msa_op, 0, msa_ctc_op, 0, 0, msa_elm_op), RD | RE},
82 	[insn_dins]	= {M(spec3_op, 0, 0, 0, 0, dins_op), RS | RT | RD | RE},
83 	[insn_dinsm]	= {M(spec3_op, 0, 0, 0, 0, dinsm_op), RS | RT | RD | RE},
84 	[insn_dinsu]	= {M(spec3_op, 0, 0, 0, 0, dinsu_op), RS | RT | RD | RE},
95 	[insn_drotr]	= {M(spec_op, 1, 0, 0, 0, dsrl_op), RT | RD | RE},
96 	[insn_drotr32]	= {M(spec_op, 1, 0, 0, 0, dsrl32_op), RT | RD | RE},
99 	[insn_dsll]	= {M(spec_op, 0, 0, 0, 0, dsll_op), RT | RD | RE},
100 	[insn_dsll32]	= {M(spec_op, 0, 0, 0, 0, dsll32_op), RT | RD | RE},
102 	[insn_dsra]	= {M(spec_op, 0, 0, 0, 0, dsra_op), RT | RD | RE},
103 	[insn_dsra32]	= {M(spec_op, 0, 0, 0, 0, dsra32_op), RT | RD | RE},
105 	[insn_dsrl]	= {M(spec_op, 0, 0, 0, 0, dsrl_op), RT | RD | RE},
106 	[insn_dsrl32]	= {M(spec_op, 0, 0, 0, 0, dsrl32_op), RT | RD | RE},
110 	[insn_ext]	= {M(spec3_op, 0, 0, 0, 0, ext_op), RS | RT | RD | RE},
111 	[insn_ins]	= {M(spec3_op, 0, 0, 0, 0, ins_op), RS | RT | RD | RE},
170 	[insn_rotr]	= {M(spec_op, 1, 0, 0, 0, srl_op),  RT | RD | RE},
183 	[insn_sll]	= {M(spec_op, 0, 0, 0, 0, sll_op),  RT | RD | RE},
189 	[insn_sra]	= {M(spec_op, 0, 0, 0, 0, sra_op),  RT | RD | RE},
191 	[insn_srl]	= {M(spec_op, 0, 0, 0, 0, srl_op),  RT | RD | RE},
195 	[insn_sync]	= {M(spec_op, 0, 0, 0, 0, sync_op), RE},
212 	WARN(arg > 0x1ffff || arg < -0x20000,  in build_bimm()
213 	     KERN_WARNING "Micro-assembler field overflow\n");  in build_bimm()
215 	WARN(arg & 0x3, KERN_WARNING "Invalid micro-assembler branch target\n");  in build_bimm()
223 	     KERN_WARNING "Micro-assembler field overflow\n");  in build_jimm()
241 		panic("Unsupported Micro-assembler instruction %d", opc);  in build_insn()
245 	op = ip->match;  in build_insn()
247 	if (ip->fields & RS)  in build_insn()
249 	if (ip->fields & RT)  in build_insn()
251 	if (ip->fields & RD)  in build_insn()
253 	if (ip->fields & RE)  in build_insn()
255 	if (ip->fields & SIMM)  in build_insn()
257 	if (ip->fields & UIMM)  in build_insn()
259 	if (ip->fields & BIMM)  in build_insn()
261 	if (ip->fields & JIMM)  in build_insn()
263 	if (ip->fields & FUNC)  in build_insn()
265 	if (ip->fields & SET)  in build_insn()
267 	if (ip->fields & SCIMM)  in build_insn()
269 	if (ip->fields & SIMM9)  in build_insn()
280 	long laddr = (long)lab->addr;  in __resolve_relocs()
281 	long raddr = (long)rel->addr;  in __resolve_relocs()
283 	switch (rel->type) {  in __resolve_relocs()
285 		*rel->addr |= build_bimm(laddr - (raddr + 4));  in __resolve_relocs()
289 		panic("Unsupported Micro-assembler relocation %d",  in __resolve_relocs()
290 		      rel->type);  in __resolve_relocs()