1 // SPDX-License-Identifier: GPL-2.0
24 	u64 asid;  in get_new_mmu_context()  local
34 	asid = asid_cache(cpu);  in get_new_mmu_context()
36 	if (!((asid += cpu_asid_inc()) & cpu_asid_mask(&cpu_data[cpu]))) {  in get_new_mmu_context()
39 		local_flush_tlb_all();	/* start new asid cycle */  in get_new_mmu_context()
42 	set_cpu_context(cpu, mm, asid);  in get_new_mmu_context()
43 	asid_cache(cpu) = asid;  in get_new_mmu_context()
58 	/* Check if our ASID is of an older version and thus invalid */  in check_mmu_context()
94 	 * context-switch  in flush_context()
146 		 * We had a valid MMID in a previous life, so try to re-use  in get_new_mmid()
182 	u64 ctx, old_active_mmid;  in check_switch_mmu_context()  local
192 	 * MMID switch fast-path, to avoid acquiring cpu_mmid_lock when it's  in check_switch_mmu_context()
195 	 * The memory ordering here is subtle. If our active_mmids is non-zero  in check_switch_mmu_context()
200 	 * - We get a zero back from the cmpxchg and end up waiting on  in check_switch_mmu_context()
205 	 * - We get a valid MMID back from the cmpxchg, which means the  in check_switch_mmu_context()
209 	ctx = cpu_context(cpu, mm);  in check_switch_mmu_context()
212 	    !asid_versions_eq(cpu, ctx, atomic64_read(&mmid_version)) ||  in check_switch_mmu_context()
213 	    !cmpxchg_relaxed(&cpu_data[cpu].asid_cache, old_active_mmid, ctx)) {  in check_switch_mmu_context()
216 		ctx = cpu_context(cpu, mm);  in check_switch_mmu_context()
217 		if (!asid_versions_eq(cpu, ctx, atomic64_read(&mmid_version)))  in check_switch_mmu_context()
218 			ctx = get_new_mmid(mm);  in check_switch_mmu_context()
220 		WRITE_ONCE(cpu_data[cpu].asid_cache, ctx);  in check_switch_mmu_context()
236 	write_c0_memorymapid(ctx & cpu_asid_mask(&boot_cpu_data));  in check_switch_mmu_context()
263 	TLBMISS_HANDLER_SETUP_PGD(mm->pgd);  in check_switch_mmu_context()