Lines Matching refs:dec_insn
424 int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, in isBranchInstr() argument
427 union mips_instruction insn = (union mips_instruction)dec_insn.insn; in isBranchInstr()
439 regs->cp0_epc + dec_insn.pc_inc + in isBranchInstr()
440 dec_insn.next_pc_inc; in isBranchInstr()
460 dec_insn.pc_inc + in isBranchInstr()
461 dec_insn.next_pc_inc; in isBranchInstr()
470 dec_insn.pc_inc + in isBranchInstr()
474 dec_insn.pc_inc + in isBranchInstr()
475 dec_insn.next_pc_inc; in isBranchInstr()
484 dec_insn.pc_inc + in isBranchInstr()
485 dec_insn.next_pc_inc; in isBranchInstr()
494 dec_insn.pc_inc + in isBranchInstr()
498 dec_insn.pc_inc + in isBranchInstr()
499 dec_insn.next_pc_inc; in isBranchInstr()
508 dec_insn.pc_inc + in isBranchInstr()
509 dec_insn.next_pc_inc; in isBranchInstr()
512 *contpc = regs->cp0_epc + dec_insn.pc_inc; in isBranchInstr()
527 dec_insn.pc_inc + in isBranchInstr()
531 dec_insn.pc_inc + in isBranchInstr()
532 dec_insn.next_pc_inc; in isBranchInstr()
542 dec_insn.pc_inc + in isBranchInstr()
546 dec_insn.pc_inc + in isBranchInstr()
547 dec_insn.next_pc_inc; in isBranchInstr()
572 dec_insn.pc_inc; in isBranchInstr()
573 *contpc = regs->cp0_epc + dec_insn.pc_inc + in isBranchInstr()
574 dec_insn.next_pc_inc; in isBranchInstr()
580 dec_insn.pc_inc + in isBranchInstr()
584 dec_insn.pc_inc + in isBranchInstr()
585 dec_insn.next_pc_inc; in isBranchInstr()
610 dec_insn.pc_inc; in isBranchInstr()
611 *contpc = regs->cp0_epc + dec_insn.pc_inc + in isBranchInstr()
612 dec_insn.next_pc_inc; in isBranchInstr()
619 dec_insn.pc_inc + in isBranchInstr()
623 dec_insn.pc_inc + in isBranchInstr()
624 dec_insn.next_pc_inc; in isBranchInstr()
632 *contpc = regs->cp0_epc + dec_insn.pc_inc + in isBranchInstr()
633 dec_insn.next_pc_inc; in isBranchInstr()
670 *contpc = regs->cp0_epc + dec_insn.pc_inc + in isBranchInstr()
671 dec_insn.next_pc_inc; in isBranchInstr()
678 *contpc = regs->cp0_epc + dec_insn.pc_inc + in isBranchInstr()
679 dec_insn.next_pc_inc; in isBranchInstr()
685 *contpc = regs->cp0_epc + dec_insn.pc_inc + in isBranchInstr()
686 dec_insn.next_pc_inc; in isBranchInstr()
694 *contpc = regs->cp0_epc + dec_insn.pc_inc + in isBranchInstr()
695 dec_insn.next_pc_inc; in isBranchInstr()
718 dec_insn.pc_inc + in isBranchInstr()
722 dec_insn.pc_inc + in isBranchInstr()
723 dec_insn.next_pc_inc; in isBranchInstr()
747 dec_insn.pc_inc + in isBranchInstr()
751 dec_insn.pc_inc + in isBranchInstr()
752 dec_insn.next_pc_inc; in isBranchInstr()
758 dec_insn.pc_inc + in isBranchInstr()
762 dec_insn.pc_inc + in isBranchInstr()
763 dec_insn.next_pc_inc; in isBranchInstr()
972 struct mm_decoded_insn dec_insn, void __user **fault_addr) in cop1Emulate() argument
974 unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc; in cop1Emulate()
989 if (!cpu_has_mmips && dec_insn.micro_mips_mode) in cop1Emulate()
994 if (dec_insn.micro_mips_mode) { in cop1Emulate()
995 if (!mm_isBranchInstr(xcp, dec_insn, &contpc)) in cop1Emulate()
998 if (!isBranchInstr(xcp, dec_insn, &contpc)) in cop1Emulate()
1016 ir = dec_insn.next_insn; /* process delay slot instr */ in cop1Emulate()
1017 pc_inc = dec_insn.next_pc_inc; in cop1Emulate()
1019 ir = dec_insn.insn; /* process current instr */ in cop1Emulate()
1020 pc_inc = dec_insn.pc_inc; in cop1Emulate()
1033 if (dec_insn.micro_mips_mode) { in cop1Emulate()
1246 xcp->cp0_epc += dec_insn.pc_inc; in cop1Emulate()
1249 ir = dec_insn.next_insn; in cop1Emulate()
1250 if (dec_insn.micro_mips_mode) { in cop1Emulate()
1254 if ((dec_insn.next_pc_inc == 2) || in cop1Emulate()
1264 if (dec_insn.next_pc_inc == 2) in cop1Emulate()
1339 xcp->cp0_epc += dec_insn.pc_inc; in cop1Emulate()
1340 contpc += dec_insn.pc_inc; in cop1Emulate()
2841 struct mm_decoded_insn dec_insn; in fpu_emulator_cop1Handler() local
2874 dec_insn.insn = (*instr_ptr << 16) | in fpu_emulator_cop1Handler()
2877 dec_insn.pc_inc = 2; in fpu_emulator_cop1Handler()
2880 dec_insn.insn = (*instr_ptr << 16) | in fpu_emulator_cop1Handler()
2883 dec_insn.pc_inc = 4; in fpu_emulator_cop1Handler()
2889 dec_insn.next_insn = (*instr_ptr << 16) | in fpu_emulator_cop1Handler()
2892 dec_insn.next_pc_inc = 2; in fpu_emulator_cop1Handler()
2894 dec_insn.next_insn = (*instr_ptr << 16) | in fpu_emulator_cop1Handler()
2897 dec_insn.next_pc_inc = 4; in fpu_emulator_cop1Handler()
2899 dec_insn.micro_mips_mode = 1; in fpu_emulator_cop1Handler()
2901 if ((get_user(dec_insn.insn, in fpu_emulator_cop1Handler()
2903 (get_user(dec_insn.next_insn, in fpu_emulator_cop1Handler()
2908 dec_insn.pc_inc = 4; in fpu_emulator_cop1Handler()
2909 dec_insn.next_pc_inc = 4; in fpu_emulator_cop1Handler()
2910 dec_insn.micro_mips_mode = 0; in fpu_emulator_cop1Handler()
2913 if ((dec_insn.insn == 0) || in fpu_emulator_cop1Handler()
2914 ((dec_insn.pc_inc == 2) && in fpu_emulator_cop1Handler()
2915 ((dec_insn.insn & 0xffff) == MM_NOP16))) in fpu_emulator_cop1Handler()
2916 xcp->cp0_epc += dec_insn.pc_inc; /* Skip NOPs */ in fpu_emulator_cop1Handler()
2922 sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr); in fpu_emulator_cop1Handler()