Lines Matching refs:MIPSInst_RT
858 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
868 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
876 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
887 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
898 if (MIPSInst_RT(ir))
899 xcp->regs[MIPSInst_RT(ir)] = value;
912 if (MIPSInst_RT(ir) == 0)
915 value = xcp->regs[MIPSInst_RT(ir)];
920 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
931 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
942 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
951 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
1064 DITOREG(dval, MIPSInst_RT(ir));
1071 DIFROMREG(dval, MIPSInst_RT(ir));
1098 SITOREG(wval, MIPSInst_RT(ir));
1105 SIFROMREG(wval, MIPSInst_RT(ir));
1125 if (MIPSInst_RT(ir) != 0) {
1126 DIFROMREG(xcp->regs[MIPSInst_RT(ir)],
1136 DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1144 if (MIPSInst_RT(ir) != 0) {
1145 SIFROMHREG(xcp->regs[MIPSInst_RT(ir)],
1155 SITOHREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1160 if (MIPSInst_RT(ir) != 0) {
1161 SIFROMREG(xcp->regs[MIPSInst_RT(ir)],
1168 SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1191 fpr = ¤t->thread.fpu.fpr[MIPSInst_RT(ir)];
1210 cbit = fpucondbit[MIPSInst_RT(ir) >> 2];
1216 switch (MIPSInst_RT(ir) & 3) {
1374 cond = fpucondbit[MIPSInst_RT(ir) >> 2];
1375 if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0))