51 	u32 hi, lo;  in divil_lbar_enable()  local
59 		_rdmsr(DIVIL_MSR_REG(offset), &hi, &lo);  in divil_lbar_enable()
60 		hi |= 0x01;  in divil_lbar_enable()
61 		_wrmsr(DIVIL_MSR_REG(offset), hi, lo);  in divil_lbar_enable()
70 	u32 hi, lo;  in divil_lbar_disable()  local
74 		_rdmsr(DIVIL_MSR_REG(offset), &hi, &lo);  in divil_lbar_disable()
75 		hi &= ~0x01;  in divil_lbar_disable()
76 		_wrmsr(DIVIL_MSR_REG(offset), hi, lo);  in divil_lbar_disable()
86 	u32 hi = 0, lo = value;  in pci_isa_write_bar()  local
89 		_rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);  in pci_isa_write_bar()
91 		_wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);  in pci_isa_write_bar()
94 		hi = 0x0000f001;  in pci_isa_write_bar()
96 		_wrmsr(divil_msr_reg[n], hi, lo);  in pci_isa_write_bar()
99 		hi = ((value & 0x000ffffc) << 12) |  in pci_isa_write_bar()
102 		_wrmsr(sb_msr_reg[n], hi, lo);  in pci_isa_write_bar()
113 	u32 hi, lo;  in pci_isa_read_bar()  local
115 	_rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);  in pci_isa_read_bar()
119 		_wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);  in pci_isa_read_bar()
121 		_rdmsr(divil_msr_reg[n], &hi, &lo);  in pci_isa_read_bar()
136 	u32 hi = 0, lo = value;  in pci_isa_write_reg()  local
147 		_rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);  in pci_isa_write_reg()
166 		_wrmsr(SB_MSR_REG(SB_ERROR), hi, lo);  in pci_isa_write_reg()
170 		_rdmsr(SB_MSR_REG(SB_CTRL), &hi, &lo);  in pci_isa_write_reg()
171 		hi &= 0xffffff00;  in pci_isa_write_reg()
172 		hi |= (value >> 8);  in pci_isa_write_reg()
173 		_wrmsr(SB_MSR_REG(SB_CTRL), hi, lo);  in pci_isa_write_reg()
194 		_rdmsr(DIVIL_MSR_REG(PIC_YSEL_HIGH), &hi, &lo);  in pci_isa_write_reg()
199 		_wrmsr(DIVIL_MSR_REG(PIC_YSEL_HIGH), hi, lo);  in pci_isa_write_reg()
202 		_rdmsr(DIVIL_MSR_REG(PIC_YSEL_HIGH), &hi, &lo);  in pci_isa_write_reg()
207 		_wrmsr(DIVIL_MSR_REG(PIC_YSEL_HIGH), hi, lo);  in pci_isa_write_reg()
212 			_rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);  in pci_isa_write_reg()
214 			_wrmsr(SB_MSR_REG(SB_ERROR), hi, lo);  in pci_isa_write_reg()
231 	u32 hi, lo;  in pci_isa_read_reg()  local
241 		_rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_SMB), &hi, &lo);  in pci_isa_read_reg()
242 		if (hi & 0x01)  in pci_isa_read_reg()
250 		_rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);  in pci_isa_read_reg()
261 		_rdmsr(GLCP_MSR_REG(GLCP_CHIP_REV_ID), &hi, &lo);  in pci_isa_read_reg()
266 		_rdmsr(SB_MSR_REG(SB_CTRL), &hi, &lo);  in pci_isa_read_reg()
267 		hi &= 0x000000f8;  in pci_isa_read_reg()
268 		conf_data = CFG_PCI_CACHE_LINE_SIZE(PCI_BRIDGE_HEADER_TYPE, hi);  in pci_isa_read_reg()