17 	u32 hi = 0, lo = value;  in pci_ide_write_reg()  local
21 		_rdmsr(GLIU_MSR_REG(GLIU_PAE), &hi, &lo);  in pci_ide_write_reg()
26 		_wrmsr(GLIU_MSR_REG(GLIU_PAE), hi, lo);  in pci_ide_write_reg()
30 			_rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);  in pci_ide_write_reg()
33 				_wrmsr(SB_MSR_REG(SB_ERROR), hi, lo);  in pci_ide_write_reg()
39 		_rdmsr(SB_MSR_REG(SB_CTRL), &hi, &lo);  in pci_ide_write_reg()
40 		hi &= 0xffffff00;  in pci_ide_write_reg()
41 		hi |= (value >> 8);  in pci_ide_write_reg()
42 		_wrmsr(SB_MSR_REG(SB_CTRL), hi, lo);  in pci_ide_write_reg()
46 			_rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);  in pci_ide_write_reg()
48 			_wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);  in pci_ide_write_reg()
50 			_rdmsr(IDE_MSR_REG(IDE_IO_BAR), &hi, &lo);  in pci_ide_write_reg()
52 			_wrmsr(IDE_MSR_REG(IDE_IO_BAR), hi, lo);  in pci_ide_write_reg()
55 			hi = 0x60000000 | ((value & 0x000ff000) >> 12);  in pci_ide_write_reg()
57 			_wrmsr(GLIU_MSR_REG(GLIU_IOD_BM2), hi, lo);  in pci_ide_write_reg()
62 			_rdmsr(DIVIL_MSR_REG(DIVIL_BALL_OPTS), &hi, &lo);  in pci_ide_write_reg()
64 			_wrmsr(DIVIL_MSR_REG(DIVIL_BALL_OPTS), hi, lo);  in pci_ide_write_reg()
66 			_rdmsr(IDE_MSR_REG(IDE_CFG), &hi, &lo);  in pci_ide_write_reg()
68 			_wrmsr(IDE_MSR_REG(IDE_CFG), hi, lo);  in pci_ide_write_reg()
72 		_rdmsr(IDE_MSR_REG(IDE_DTC), &hi, &lo);  in pci_ide_write_reg()
74 		_wrmsr(IDE_MSR_REG(IDE_DTC), hi, lo);  in pci_ide_write_reg()
77 		_rdmsr(IDE_MSR_REG(IDE_CAST), &hi, &lo);  in pci_ide_write_reg()
79 		_wrmsr(IDE_MSR_REG(IDE_CAST), hi, lo);  in pci_ide_write_reg()
82 		_rdmsr(IDE_MSR_REG(IDE_ETC), &hi, &lo);  in pci_ide_write_reg()
84 		_wrmsr(IDE_MSR_REG(IDE_ETC), hi, lo);  in pci_ide_write_reg()
87 		_rdmsr(IDE_MSR_REG(IDE_INTERNAL_PM), &hi, &lo);  in pci_ide_write_reg()
89 		_wrmsr(IDE_MSR_REG(IDE_INTERNAL_PM), hi, lo);  in pci_ide_write_reg()
99 	u32 hi, lo;  in pci_ide_read_reg()  local
107 		_rdmsr(IDE_MSR_REG(IDE_IO_BAR), &hi, &lo);  in pci_ide_read_reg()
110 		_rdmsr(GLIU_MSR_REG(GLIU_PAE), &hi, &lo);  in pci_ide_read_reg()
117 		_rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);  in pci_ide_read_reg()
123 		_rdmsr(IDE_MSR_REG(IDE_CAP), &hi, &lo);  in pci_ide_read_reg()
128 		_rdmsr(SB_MSR_REG(SB_CTRL), &hi, &lo);  in pci_ide_read_reg()
129 		hi &= 0x000000f8;  in pci_ide_read_reg()
130 		conf_data = CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE, hi);  in pci_ide_read_reg()
133 		_rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);  in pci_ide_read_reg()
138 			_wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);  in pci_ide_read_reg()
140 			_rdmsr(IDE_MSR_REG(IDE_IO_BAR), &hi, &lo);  in pci_ide_read_reg()
164 		_rdmsr(IDE_MSR_REG(IDE_CFG), &hi, &lo);  in pci_ide_read_reg()
168 		_rdmsr(IDE_MSR_REG(IDE_DTC), &hi, &lo);  in pci_ide_read_reg()
172 		_rdmsr(IDE_MSR_REG(IDE_CAST), &hi, &lo);  in pci_ide_read_reg()
176 		_rdmsr(IDE_MSR_REG(IDE_ETC), &hi, &lo);  in pci_ide_read_reg()
180 		_rdmsr(IDE_MSR_REG(IDE_INTERNAL_PM), &hi, &lo);  in pci_ide_read_reg()