Lines Matching +full:1 +full:v1

63 	sltu	v1, sum, reg;					\
64 	ADD	sum, v1;					\
71 	sltu	v1, sum, reg;					\
72 	addu	sum, v1;					\
77 	LOAD	_t1, (offset + UNIT(1))(src);			\
189 	beqz	t8, 1f
203 1:
204 	beqz	t2, 1f
212 1:
240 	beqz	t0, 1f
251 1:	move	t1, zero
252 	beqz	t0, 1f
253 	 andi	t0, a1, 1
259 1:	beqz	t0, 1f
270 1:	ADDC(sum, t1)
274 	dsll32	v1, sum, 0
275 	daddu	sum, v1
276 	sltu	v1, sum, v1
278 	addu	sum, v1
286 	wsbh	v1, sum
287 	movn	sum, v1, t7
290 	beqz	t7, 1f			/* odd buffer alignment? */
291 	 lui	v1, 0x00ff
292 	addu	v1, 0x00ff
293 	and	t0, sum, v1
296 	and	sum, sum, v1
298 1:
329 #define LD_INSN 1
331 #define LEGACY_MODE 1
333 #define USEROP   1
428 #define REST(unit)  (FIRST(unit)+NBYTES-1)
430 #define ADDRMASK (NBYTES-1)
435 	.set	at=v1
440 	li	sum, -1
471 1:
473 	LOAD(t1, UNIT(1)(src))
484 	STORE(t1, UNIT(1)(dst))
500 	bgez	len, 1b
512 	 and	rem, len, (NBYTES-1)	# rem = len % NBYTES
517 	LOAD(t1, UNIT(1)(src))
524 	STORE(t1, UNIT(1)(dst))
540 1:
548 	bne	rem, len, 1b
570 	STREST(t0, -1(t1))
606 	 and	rem, len, (4*NBYTES-1)	 # rem = len % 4*NBYTES
607 1:
611  * It's OK to load FIRST(N+1) before REST(N) because the two addresses
615 	LDFIRST(t1, FIRST(1)(src))
618 	LDREST(t1, REST(1)(src))
629 	STORE(t1, UNIT(1)(dst))
637 	bne	len, rem, 1b
642 	 and	rem, len, NBYTES-1  # rem = len % NBYTES
645 1:
654 	bne	len, rem, 1b
666 #define SHIFT_START 8*(NBYTES-1)
673 	SUB	len, len, 1;		\
681 	COPY_BYTE(1)
689 	SUB	len, len, 1
700 	dsll32	v1, sum, 0
701 	daddu	sum, v1
702 	sltu	v1, sum, v1
704 	addu	sum, v1
711 	wsbh	v1, sum
712 	movn	sum, v1, odd
715 	beqz	odd, 1f			/* odd buffer alignment? */
716 	 lui	v1, 0x00ff
717 	addu	v1, 0x00ff
718 	and	t0, sum, v1
721 	and	sum, sum, v1
723 1: