Lines Matching +full:reg +full:- +full:addr
18 * only the performance is affected. Much worse is that such code is non-
30 * option in your user programs - I discourage the use of the software
31 * emulation strongly - use the following code in your userland stuff:
92 #include <asm/unaligned-emul.h>
97 #include "access-helper.h"
113 void __user *addr, unsigned int *pc) in emulate_load_store_insn() argument
121 orig31 = regs->regs[31]; in emulate_load_store_insn()
133 * can assume therefore that the code is MIPS-aware and in emulate_load_store_insn()
171 if (user && !access_ok(addr, 4)) in emulate_load_store_insn()
173 LoadW(addr, value, res); in emulate_load_store_insn()
177 regs->regs[insn.mxu_lx_format.rd] = value; in emulate_load_store_insn()
180 if (user && !access_ok(addr, 2)) in emulate_load_store_insn()
182 LoadHW(addr, value, res); in emulate_load_store_insn()
186 regs->regs[insn.dsp_format.rd] = value; in emulate_load_store_insn()
189 if (user && !access_ok(addr, 2)) in emulate_load_store_insn()
191 LoadHWU(addr, value, res); in emulate_load_store_insn()
195 regs->regs[insn.dsp_format.rd] = value; in emulate_load_store_insn()
209 if (user && !access_ok(addr, 4)) in emulate_load_store_insn()
211 LoadW(addr, value, res); in emulate_load_store_insn()
215 regs->regs[insn.dsp_format.rd] = value; in emulate_load_store_insn()
218 if (user && !access_ok(addr, 2)) in emulate_load_store_insn()
220 LoadHW(addr, value, res); in emulate_load_store_insn()
224 regs->regs[insn.dsp_format.rd] = value; in emulate_load_store_insn()
239 if (!access_ok(addr, 2)) in emulate_load_store_insn()
241 LoadHWE(addr, value, res); in emulate_load_store_insn()
245 regs->regs[insn.spec3_format.rt] = value; in emulate_load_store_insn()
248 if (!access_ok(addr, 4)) in emulate_load_store_insn()
250 LoadWE(addr, value, res); in emulate_load_store_insn()
254 regs->regs[insn.spec3_format.rt] = value; in emulate_load_store_insn()
257 if (!access_ok(addr, 2)) in emulate_load_store_insn()
259 LoadHWUE(addr, value, res); in emulate_load_store_insn()
263 regs->regs[insn.spec3_format.rt] = value; in emulate_load_store_insn()
266 if (!access_ok(addr, 2)) in emulate_load_store_insn()
269 value = regs->regs[insn.spec3_format.rt]; in emulate_load_store_insn()
270 StoreHWE(addr, value, res); in emulate_load_store_insn()
275 if (!access_ok(addr, 4)) in emulate_load_store_insn()
278 value = regs->regs[insn.spec3_format.rt]; in emulate_load_store_insn()
279 StoreWE(addr, value, res); in emulate_load_store_insn()
290 if (user && !access_ok(addr, 2)) in emulate_load_store_insn()
294 LoadHWE(addr, value, res); in emulate_load_store_insn()
296 LoadHW(addr, value, res); in emulate_load_store_insn()
301 regs->regs[insn.i_format.rt] = value; in emulate_load_store_insn()
305 if (user && !access_ok(addr, 4)) in emulate_load_store_insn()
309 LoadWE(addr, value, res); in emulate_load_store_insn()
311 LoadW(addr, value, res); in emulate_load_store_insn()
316 regs->regs[insn.i_format.rt] = value; in emulate_load_store_insn()
320 if (user && !access_ok(addr, 2)) in emulate_load_store_insn()
324 LoadHWUE(addr, value, res); in emulate_load_store_insn()
326 LoadHWU(addr, value, res); in emulate_load_store_insn()
331 regs->regs[insn.i_format.rt] = value; in emulate_load_store_insn()
337 * A 32-bit kernel might be running on a 64-bit processor. But in emulate_load_store_insn()
338 * if we're on a 32-bit processor and an i-cache incoherency in emulate_load_store_insn()
339 * or race makes us see a 64-bit instruction here the sdl/sdr in emulate_load_store_insn()
340 * would blow up, so for now we don't handle unaligned 64-bit in emulate_load_store_insn()
341 * instructions on 32-bit kernels. in emulate_load_store_insn()
343 if (user && !access_ok(addr, 4)) in emulate_load_store_insn()
346 LoadWU(addr, value, res); in emulate_load_store_insn()
350 regs->regs[insn.i_format.rt] = value; in emulate_load_store_insn()
354 /* Cannot handle 64-bit instructions in 32-bit kernel */ in emulate_load_store_insn()
360 * A 32-bit kernel might be running on a 64-bit processor. But in emulate_load_store_insn()
361 * if we're on a 32-bit processor and an i-cache incoherency in emulate_load_store_insn()
362 * or race makes us see a 64-bit instruction here the sdl/sdr in emulate_load_store_insn()
363 * would blow up, so for now we don't handle unaligned 64-bit in emulate_load_store_insn()
364 * instructions on 32-bit kernels. in emulate_load_store_insn()
366 if (user && !access_ok(addr, 8)) in emulate_load_store_insn()
369 LoadDW(addr, value, res); in emulate_load_store_insn()
373 regs->regs[insn.i_format.rt] = value; in emulate_load_store_insn()
377 /* Cannot handle 64-bit instructions in 32-bit kernel */ in emulate_load_store_insn()
381 if (user && !access_ok(addr, 2)) in emulate_load_store_insn()
385 value = regs->regs[insn.i_format.rt]; in emulate_load_store_insn()
388 StoreHWE(addr, value, res); in emulate_load_store_insn()
390 StoreHW(addr, value, res); in emulate_load_store_insn()
397 if (user && !access_ok(addr, 4)) in emulate_load_store_insn()
401 value = regs->regs[insn.i_format.rt]; in emulate_load_store_insn()
404 StoreWE(addr, value, res); in emulate_load_store_insn()
406 StoreW(addr, value, res); in emulate_load_store_insn()
415 * A 32-bit kernel might be running on a 64-bit processor. But in emulate_load_store_insn()
416 * if we're on a 32-bit processor and an i-cache incoherency in emulate_load_store_insn()
417 * or race makes us see a 64-bit instruction here the sdl/sdr in emulate_load_store_insn()
418 * would blow up, so for now we don't handle unaligned 64-bit in emulate_load_store_insn()
419 * instructions on 32-bit kernels. in emulate_load_store_insn()
421 if (user && !access_ok(addr, 8)) in emulate_load_store_insn()
425 value = regs->regs[insn.i_format.rt]; in emulate_load_store_insn()
426 StoreDW(addr, value, res); in emulate_load_store_insn()
432 /* Cannot handle 64-bit instructions in 32-bit kernel */ in emulate_load_store_insn()
447 res = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1, in emulate_load_store_insn()
479 fpr = ¤t->thread.fpu.fpr[wd]; in emulate_load_store_insn()
483 if (!access_ok(addr, sizeof(*fpr))) in emulate_load_store_insn()
498 res = __copy_from_user_inatomic(fpr, addr, in emulate_load_store_insn()
519 if (!access_ok(addr, sizeof(*fpr))) in emulate_load_store_insn()
532 res = __copy_to_user_inatomic(addr, fpr, sizeof(*fpr)); in emulate_load_store_insn()
586 regs->cp0_epc = origpc; in emulate_load_store_insn()
587 regs->regs[31] = orig31; in emulate_load_store_insn()
609 /* Recode table from 16-bit register notation to 32-bit GPR. */
612 /* Recode table from 16-bit STORE register notation to 32-bit GPR. */
616 void __user *addr) in emulate_load_store_microMIPS() argument
621 unsigned int reg = 0, rvar; in emulate_load_store_microMIPS() local
631 origpc = regs->cp0_epc; in emulate_load_store_microMIPS()
632 orig31 = regs->regs[31]; in emulate_load_store_microMIPS()
639 pc16 = (unsigned short __user *)msk_isa16_mode(regs->cp0_epc); in emulate_load_store_microMIPS()
642 contpc = regs->cp0_epc + 2; in emulate_load_store_microMIPS()
649 contpc = regs->cp0_epc + 4; in emulate_load_store_microMIPS()
680 reg = insn.mm_x_format.rd; in emulate_load_store_microMIPS()
689 reg = insn.mm_m_format.rd; in emulate_load_store_microMIPS()
690 if (reg == 31) in emulate_load_store_microMIPS()
693 if (user && !access_ok(addr, 8)) in emulate_load_store_microMIPS()
696 LoadW(addr, value, res); in emulate_load_store_microMIPS()
699 regs->regs[reg] = value; in emulate_load_store_microMIPS()
700 addr += 4; in emulate_load_store_microMIPS()
701 LoadW(addr, value, res); in emulate_load_store_microMIPS()
704 regs->regs[reg + 1] = value; in emulate_load_store_microMIPS()
708 reg = insn.mm_m_format.rd; in emulate_load_store_microMIPS()
709 if (reg == 31) in emulate_load_store_microMIPS()
712 if (user && !access_ok(addr, 8)) in emulate_load_store_microMIPS()
715 value = regs->regs[reg]; in emulate_load_store_microMIPS()
716 StoreW(addr, value, res); in emulate_load_store_microMIPS()
719 addr += 4; in emulate_load_store_microMIPS()
720 value = regs->regs[reg + 1]; in emulate_load_store_microMIPS()
721 StoreW(addr, value, res); in emulate_load_store_microMIPS()
728 reg = insn.mm_m_format.rd; in emulate_load_store_microMIPS()
729 if (reg == 31) in emulate_load_store_microMIPS()
732 if (user && !access_ok(addr, 16)) in emulate_load_store_microMIPS()
735 LoadDW(addr, value, res); in emulate_load_store_microMIPS()
738 regs->regs[reg] = value; in emulate_load_store_microMIPS()
739 addr += 8; in emulate_load_store_microMIPS()
740 LoadDW(addr, value, res); in emulate_load_store_microMIPS()
743 regs->regs[reg + 1] = value; in emulate_load_store_microMIPS()
751 reg = insn.mm_m_format.rd; in emulate_load_store_microMIPS()
752 if (reg == 31) in emulate_load_store_microMIPS()
755 if (user && !access_ok(addr, 16)) in emulate_load_store_microMIPS()
758 value = regs->regs[reg]; in emulate_load_store_microMIPS()
759 StoreDW(addr, value, res); in emulate_load_store_microMIPS()
762 addr += 8; in emulate_load_store_microMIPS()
763 value = regs->regs[reg + 1]; in emulate_load_store_microMIPS()
764 StoreDW(addr, value, res); in emulate_load_store_microMIPS()
773 reg = insn.mm_m_format.rd; in emulate_load_store_microMIPS()
774 rvar = reg & 0xf; in emulate_load_store_microMIPS()
775 if ((rvar > 9) || !reg) in emulate_load_store_microMIPS()
777 if (reg & 0x10) { in emulate_load_store_microMIPS()
778 if (user && !access_ok(addr, 4 * (rvar + 1))) in emulate_load_store_microMIPS()
781 if (user && !access_ok(addr, 4 * rvar)) in emulate_load_store_microMIPS()
786 for (i = 16; rvar; rvar--, i++) { in emulate_load_store_microMIPS()
787 LoadW(addr, value, res); in emulate_load_store_microMIPS()
790 addr += 4; in emulate_load_store_microMIPS()
791 regs->regs[i] = value; in emulate_load_store_microMIPS()
793 if ((reg & 0xf) == 9) { in emulate_load_store_microMIPS()
794 LoadW(addr, value, res); in emulate_load_store_microMIPS()
797 addr += 4; in emulate_load_store_microMIPS()
798 regs->regs[30] = value; in emulate_load_store_microMIPS()
800 if (reg & 0x10) { in emulate_load_store_microMIPS()
801 LoadW(addr, value, res); in emulate_load_store_microMIPS()
804 regs->regs[31] = value; in emulate_load_store_microMIPS()
809 reg = insn.mm_m_format.rd; in emulate_load_store_microMIPS()
810 rvar = reg & 0xf; in emulate_load_store_microMIPS()
811 if ((rvar > 9) || !reg) in emulate_load_store_microMIPS()
813 if (reg & 0x10) { in emulate_load_store_microMIPS()
814 if (user && !access_ok(addr, 4 * (rvar + 1))) in emulate_load_store_microMIPS()
817 if (user && !access_ok(addr, 4 * rvar)) in emulate_load_store_microMIPS()
822 for (i = 16; rvar; rvar--, i++) { in emulate_load_store_microMIPS()
823 value = regs->regs[i]; in emulate_load_store_microMIPS()
824 StoreW(addr, value, res); in emulate_load_store_microMIPS()
827 addr += 4; in emulate_load_store_microMIPS()
829 if ((reg & 0xf) == 9) { in emulate_load_store_microMIPS()
830 value = regs->regs[30]; in emulate_load_store_microMIPS()
831 StoreW(addr, value, res); in emulate_load_store_microMIPS()
834 addr += 4; in emulate_load_store_microMIPS()
836 if (reg & 0x10) { in emulate_load_store_microMIPS()
837 value = regs->regs[31]; in emulate_load_store_microMIPS()
838 StoreW(addr, value, res); in emulate_load_store_microMIPS()
846 reg = insn.mm_m_format.rd; in emulate_load_store_microMIPS()
847 rvar = reg & 0xf; in emulate_load_store_microMIPS()
848 if ((rvar > 9) || !reg) in emulate_load_store_microMIPS()
850 if (reg & 0x10) { in emulate_load_store_microMIPS()
851 if (user && !access_ok(addr, 8 * (rvar + 1))) in emulate_load_store_microMIPS()
854 if (user && !access_ok(addr, 8 * rvar)) in emulate_load_store_microMIPS()
860 for (i = 16; rvar; rvar--, i++) { in emulate_load_store_microMIPS()
861 LoadDW(addr, value, res); in emulate_load_store_microMIPS()
864 addr += 4; in emulate_load_store_microMIPS()
865 regs->regs[i] = value; in emulate_load_store_microMIPS()
867 if ((reg & 0xf) == 9) { in emulate_load_store_microMIPS()
868 LoadDW(addr, value, res); in emulate_load_store_microMIPS()
871 addr += 8; in emulate_load_store_microMIPS()
872 regs->regs[30] = value; in emulate_load_store_microMIPS()
874 if (reg & 0x10) { in emulate_load_store_microMIPS()
875 LoadDW(addr, value, res); in emulate_load_store_microMIPS()
878 regs->regs[31] = value; in emulate_load_store_microMIPS()
887 reg = insn.mm_m_format.rd; in emulate_load_store_microMIPS()
888 rvar = reg & 0xf; in emulate_load_store_microMIPS()
889 if ((rvar > 9) || !reg) in emulate_load_store_microMIPS()
891 if (reg & 0x10) { in emulate_load_store_microMIPS()
892 if (user && !access_ok(addr, 8 * (rvar + 1))) in emulate_load_store_microMIPS()
895 if (user && !access_ok(addr, 8 * rvar)) in emulate_load_store_microMIPS()
901 for (i = 16; rvar; rvar--, i++) { in emulate_load_store_microMIPS()
902 value = regs->regs[i]; in emulate_load_store_microMIPS()
903 StoreDW(addr, value, res); in emulate_load_store_microMIPS()
906 addr += 8; in emulate_load_store_microMIPS()
908 if ((reg & 0xf) == 9) { in emulate_load_store_microMIPS()
909 value = regs->regs[30]; in emulate_load_store_microMIPS()
910 StoreDW(addr, value, res); in emulate_load_store_microMIPS()
913 addr += 8; in emulate_load_store_microMIPS()
915 if (reg & 0x10) { in emulate_load_store_microMIPS()
916 value = regs->regs[31]; in emulate_load_store_microMIPS()
917 StoreDW(addr, value, res); in emulate_load_store_microMIPS()
934 reg = insn.mm_m_format.rd; in emulate_load_store_microMIPS()
961 regs->cp0_epc = origpc; in emulate_load_store_microMIPS()
962 regs->regs[31] = orig31; in emulate_load_store_microMIPS()
968 res = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1, in emulate_load_store_microMIPS()
982 reg = insn.mm_i_format.rt; in emulate_load_store_microMIPS()
986 reg = insn.mm_i_format.rt; in emulate_load_store_microMIPS()
990 reg = insn.mm_i_format.rt; in emulate_load_store_microMIPS()
994 reg = insn.mm_i_format.rt; in emulate_load_store_microMIPS()
998 reg = insn.mm_i_format.rt; in emulate_load_store_microMIPS()
1002 reg = insn.mm_i_format.rt; in emulate_load_store_microMIPS()
1006 reg = insn.mm_i_format.rt; in emulate_load_store_microMIPS()
1012 reg = insn.mm16_m_format.rlist; in emulate_load_store_microMIPS()
1013 rvar = reg + 1; in emulate_load_store_microMIPS()
1014 if (user && !access_ok(addr, 4 * rvar)) in emulate_load_store_microMIPS()
1017 for (i = 16; rvar; rvar--, i++) { in emulate_load_store_microMIPS()
1018 LoadW(addr, value, res); in emulate_load_store_microMIPS()
1021 addr += 4; in emulate_load_store_microMIPS()
1022 regs->regs[i] = value; in emulate_load_store_microMIPS()
1024 LoadW(addr, value, res); in emulate_load_store_microMIPS()
1027 regs->regs[31] = value; in emulate_load_store_microMIPS()
1032 reg = insn.mm16_m_format.rlist; in emulate_load_store_microMIPS()
1033 rvar = reg + 1; in emulate_load_store_microMIPS()
1034 if (user && !access_ok(addr, 4 * rvar)) in emulate_load_store_microMIPS()
1037 for (i = 16; rvar; rvar--, i++) { in emulate_load_store_microMIPS()
1038 value = regs->regs[i]; in emulate_load_store_microMIPS()
1039 StoreW(addr, value, res); in emulate_load_store_microMIPS()
1042 addr += 4; in emulate_load_store_microMIPS()
1044 value = regs->regs[31]; in emulate_load_store_microMIPS()
1045 StoreW(addr, value, res); in emulate_load_store_microMIPS()
1056 reg = reg16to32[insn.mm16_rb_format.rt]; in emulate_load_store_microMIPS()
1060 reg = reg16to32[insn.mm16_rb_format.rt]; in emulate_load_store_microMIPS()
1064 reg = reg16to32st[insn.mm16_rb_format.rt]; in emulate_load_store_microMIPS()
1068 reg = reg16to32st[insn.mm16_rb_format.rt]; in emulate_load_store_microMIPS()
1072 reg = insn.mm16_r5_format.rt; in emulate_load_store_microMIPS()
1076 reg = insn.mm16_r5_format.rt; in emulate_load_store_microMIPS()
1080 reg = reg16to32[insn.mm16_r3_format.rt]; in emulate_load_store_microMIPS()
1088 if (user && !access_ok(addr, 2)) in emulate_load_store_microMIPS()
1091 LoadHW(addr, value, res); in emulate_load_store_microMIPS()
1094 regs->regs[reg] = value; in emulate_load_store_microMIPS()
1098 if (user && !access_ok(addr, 2)) in emulate_load_store_microMIPS()
1101 LoadHWU(addr, value, res); in emulate_load_store_microMIPS()
1104 regs->regs[reg] = value; in emulate_load_store_microMIPS()
1108 if (user && !access_ok(addr, 4)) in emulate_load_store_microMIPS()
1111 LoadW(addr, value, res); in emulate_load_store_microMIPS()
1114 regs->regs[reg] = value; in emulate_load_store_microMIPS()
1120 * A 32-bit kernel might be running on a 64-bit processor. But in emulate_load_store_microMIPS()
1121 * if we're on a 32-bit processor and an i-cache incoherency in emulate_load_store_microMIPS()
1122 * or race makes us see a 64-bit instruction here the sdl/sdr in emulate_load_store_microMIPS()
1123 * would blow up, so for now we don't handle unaligned 64-bit in emulate_load_store_microMIPS()
1124 * instructions on 32-bit kernels. in emulate_load_store_microMIPS()
1126 if (user && !access_ok(addr, 4)) in emulate_load_store_microMIPS()
1129 LoadWU(addr, value, res); in emulate_load_store_microMIPS()
1132 regs->regs[reg] = value; in emulate_load_store_microMIPS()
1136 /* Cannot handle 64-bit instructions in 32-bit kernel */ in emulate_load_store_microMIPS()
1142 * A 32-bit kernel might be running on a 64-bit processor. But in emulate_load_store_microMIPS()
1143 * if we're on a 32-bit processor and an i-cache incoherency in emulate_load_store_microMIPS()
1144 * or race makes us see a 64-bit instruction here the sdl/sdr in emulate_load_store_microMIPS()
1145 * would blow up, so for now we don't handle unaligned 64-bit in emulate_load_store_microMIPS()
1146 * instructions on 32-bit kernels. in emulate_load_store_microMIPS()
1148 if (user && !access_ok(addr, 8)) in emulate_load_store_microMIPS()
1151 LoadDW(addr, value, res); in emulate_load_store_microMIPS()
1154 regs->regs[reg] = value; in emulate_load_store_microMIPS()
1158 /* Cannot handle 64-bit instructions in 32-bit kernel */ in emulate_load_store_microMIPS()
1162 if (user && !access_ok(addr, 2)) in emulate_load_store_microMIPS()
1165 value = regs->regs[reg]; in emulate_load_store_microMIPS()
1166 StoreHW(addr, value, res); in emulate_load_store_microMIPS()
1172 if (user && !access_ok(addr, 4)) in emulate_load_store_microMIPS()
1175 value = regs->regs[reg]; in emulate_load_store_microMIPS()
1176 StoreW(addr, value, res); in emulate_load_store_microMIPS()
1184 * A 32-bit kernel might be running on a 64-bit processor. But in emulate_load_store_microMIPS()
1185 * if we're on a 32-bit processor and an i-cache incoherency in emulate_load_store_microMIPS()
1186 * or race makes us see a 64-bit instruction here the sdl/sdr in emulate_load_store_microMIPS()
1187 * would blow up, so for now we don't handle unaligned 64-bit in emulate_load_store_microMIPS()
1188 * instructions on 32-bit kernels. in emulate_load_store_microMIPS()
1190 if (user && !access_ok(addr, 8)) in emulate_load_store_microMIPS()
1193 value = regs->regs[reg]; in emulate_load_store_microMIPS()
1194 StoreDW(addr, value, res); in emulate_load_store_microMIPS()
1200 /* Cannot handle 64-bit instructions in 32-bit kernel */ in emulate_load_store_microMIPS()
1204 regs->cp0_epc = contpc; /* advance or branch */ in emulate_load_store_microMIPS()
1213 regs->cp0_epc = origpc; in emulate_load_store_microMIPS()
1214 regs->regs[31] = orig31; in emulate_load_store_microMIPS()
1236 static void emulate_load_store_MIPS16e(struct pt_regs *regs, void __user * addr) in emulate_load_store_MIPS16e() argument
1240 int reg; in emulate_load_store_MIPS16e() local
1249 origpc = regs->cp0_epc; in emulate_load_store_MIPS16e()
1250 orig31 = regs->regs[31]; in emulate_load_store_MIPS16e()
1279 reg = reg16to32[mips16inst.ri64.ry]; in emulate_load_store_MIPS16e()
1283 reg = reg16to32[mips16inst.ri64.ry]; in emulate_load_store_MIPS16e()
1287 reg = 29; /* GPRSP */ in emulate_load_store_MIPS16e()
1294 reg = reg16to32[mips16inst.ri.rx]; in emulate_load_store_MIPS16e()
1309 reg = reg16to32[mips16inst.ri.rx]; in emulate_load_store_MIPS16e()
1313 reg = reg16to32[mips16inst.ri.rx]; in emulate_load_store_MIPS16e()
1333 reg = 29; /* GPRSP */ in emulate_load_store_MIPS16e()
1337 reg = reg16to32[mips16inst.rri.ry]; in emulate_load_store_MIPS16e()
1349 if (user && !access_ok(addr, 2)) in emulate_load_store_MIPS16e()
1352 LoadHW(addr, value, res); in emulate_load_store_MIPS16e()
1356 regs->regs[reg] = value; in emulate_load_store_MIPS16e()
1360 if (user && !access_ok(addr, 2)) in emulate_load_store_MIPS16e()
1363 LoadHWU(addr, value, res); in emulate_load_store_MIPS16e()
1367 regs->regs[reg] = value; in emulate_load_store_MIPS16e()
1373 if (user && !access_ok(addr, 4)) in emulate_load_store_MIPS16e()
1376 LoadW(addr, value, res); in emulate_load_store_MIPS16e()
1380 regs->regs[reg] = value; in emulate_load_store_MIPS16e()
1386 * A 32-bit kernel might be running on a 64-bit processor. But in emulate_load_store_MIPS16e()
1387 * if we're on a 32-bit processor and an i-cache incoherency in emulate_load_store_MIPS16e()
1388 * or race makes us see a 64-bit instruction here the sdl/sdr in emulate_load_store_MIPS16e()
1389 * would blow up, so for now we don't handle unaligned 64-bit in emulate_load_store_MIPS16e()
1390 * instructions on 32-bit kernels. in emulate_load_store_MIPS16e()
1392 if (user && !access_ok(addr, 4)) in emulate_load_store_MIPS16e()
1395 LoadWU(addr, value, res); in emulate_load_store_MIPS16e()
1399 regs->regs[reg] = value; in emulate_load_store_MIPS16e()
1403 /* Cannot handle 64-bit instructions in 32-bit kernel */ in emulate_load_store_MIPS16e()
1410 * A 32-bit kernel might be running on a 64-bit processor. But in emulate_load_store_MIPS16e()
1411 * if we're on a 32-bit processor and an i-cache incoherency in emulate_load_store_MIPS16e()
1412 * or race makes us see a 64-bit instruction here the sdl/sdr in emulate_load_store_MIPS16e()
1413 * would blow up, so for now we don't handle unaligned 64-bit in emulate_load_store_MIPS16e()
1414 * instructions on 32-bit kernels. in emulate_load_store_MIPS16e()
1416 if (user && !access_ok(addr, 8)) in emulate_load_store_MIPS16e()
1419 LoadDW(addr, value, res); in emulate_load_store_MIPS16e()
1423 regs->regs[reg] = value; in emulate_load_store_MIPS16e()
1427 /* Cannot handle 64-bit instructions in 32-bit kernel */ in emulate_load_store_MIPS16e()
1431 if (user && !access_ok(addr, 2)) in emulate_load_store_MIPS16e()
1435 value = regs->regs[reg]; in emulate_load_store_MIPS16e()
1436 StoreHW(addr, value, res); in emulate_load_store_MIPS16e()
1443 case MIPS16e_i8_op: /* actually - MIPS16e_swrasp_func */ in emulate_load_store_MIPS16e()
1444 if (user && !access_ok(addr, 4)) in emulate_load_store_MIPS16e()
1448 value = regs->regs[reg]; in emulate_load_store_MIPS16e()
1449 StoreW(addr, value, res); in emulate_load_store_MIPS16e()
1458 * A 32-bit kernel might be running on a 64-bit processor. But in emulate_load_store_MIPS16e()
1459 * if we're on a 32-bit processor and an i-cache incoherency in emulate_load_store_MIPS16e()
1460 * or race makes us see a 64-bit instruction here the sdl/sdr in emulate_load_store_MIPS16e()
1461 * would blow up, so for now we don't handle unaligned 64-bit in emulate_load_store_MIPS16e()
1462 * instructions on 32-bit kernels. in emulate_load_store_MIPS16e()
1464 if (user && !access_ok(addr, 8)) in emulate_load_store_MIPS16e()
1468 value = regs->regs[reg]; in emulate_load_store_MIPS16e()
1469 StoreDW(addr, value, res); in emulate_load_store_MIPS16e()
1475 /* Cannot handle 64-bit instructions in 32-bit kernel */ in emulate_load_store_MIPS16e()
1494 regs->cp0_epc = origpc; in emulate_load_store_MIPS16e()
1495 regs->regs[31] = orig31; in emulate_load_store_MIPS16e()
1524 1, regs, regs->cp0_badvaddr); in do_ade()
1532 if ((regs->cp0_badvaddr >= (1UL << cpu_vmbits)) && in do_ade()
1533 (regs->cp0_badvaddr < XKSSEG)) { in do_ade()
1535 current->thread.cp0_baduaddr = regs->cp0_badvaddr; in do_ade()
1545 if (regs->cp0_badvaddr == regs->cp0_epc) in do_ade()
1561 if (get_isa16_mode(regs->cp0_epc)) { in do_ade()
1564 * 16-bit mode? in do_ade()
1566 if (regs->cp0_badvaddr == msk_isa16_mode(regs->cp0_epc)) in do_ade()
1573 (void __user *)regs->cp0_badvaddr); in do_ade()
1579 (void __user *)regs->cp0_badvaddr); in do_ade()
1590 emulate_load_store_insn(regs, (void __user *)regs->cp0_badvaddr, pc); in do_ade()