1 // SPDX-License-Identifier: GPL-2.0-or-later
19 #include <asm/mips-cps.h>
22 #include <asm/pm-cps.h>
26 #include <asm/smp-cps.h>
101 						0x0, CSEGX_SIZE - 1);  in allocate_cps_vecs()
109 							0x0, SZ_4G - 1);  in allocate_cps_vecs()
116 		return -ENOMEM;  in allocate_cps_vecs()
167 			for (v = 0; v < min_t(int, core_vpes, NR_CPUS - nvpes); v++) {  in cps_smp_setup()
191 	/* Core 0 is powered up (we're running on it) */  in cps_smp_setup()
207 	/* If we have an FPU, enroll ourselves in the FPU-full mask */  in cps_smp_setup()
221 		pr_err("core_entry address unsuitable, disabling smp-cps\n");  in cps_prepare_cpus()
225 	/* Detect whether the CCA is unsuited to multi-core SMP */  in cps_prepare_cpus()
230 		/* The CCA is coherent, multi-core is fine */  in cps_prepare_cpus()
235 		/* CCA is not coherent, multi-core is not usable */  in cps_prepare_cpus()
239 	/* Warn the user if the CCA prevents multi-core */  in cps_prepare_cpus()
355 				timeout--;  in boot_core()
373 	/* The core is now powered up */  in boot_core()
390 	struct vpe_boot_config *vpe_cfg = &core_cfg->vpe_config[vpe_id];  in cps_boot_secondary()
396 		return -ENOSYS;  in cps_boot_secondary()
398 	vpe_cfg->pc = (unsigned long)&smp_bootstrap;  in cps_boot_secondary()
399 	vpe_cfg->sp = __KSTK_TOS(idle);  in cps_boot_secondary()
400 	vpe_cfg->gp = (unsigned long)task_thread_info(idle);  in cps_boot_secondary()
402 	atomic_or(1 << cpu_vpe_id(&cpu_data[cpu]), &core_cfg->vpe_mask);  in cps_boot_secondary()
407 		/* Boot a VPE on a powered down core */  in cps_boot_secondary()
419 		/* Boot a VPE on another powered up core */  in cps_boot_secondary()
441 	/* Boot a VPE on this core */  in cps_boot_secondary()
452 	/* Disable MT - we only want to run 1 TC per VPE */  in cps_init_secondary()
483 	/* If we have an FPU, enroll ourselves in the FPU-full mask */  in cps_smp_finish()
550 		return -EINVAL;  in cps_cpu_disable()
553 	atomic_sub(1 << cpu_vpe_id(&current_cpu_data), &core_cfg->vpe_mask);  in cps_cpu_disable()
628 	 *   - Onlining the CPU again.  in cps_cleanup_dead_cpu()
629 	 *   - Powering down the core if another VPE within it is offlined.  in cps_cleanup_dead_cpu()
630 	 *   - A sibling VPE entering a non-coherent state.  in cps_cleanup_dead_cpu()
632 	 * In the non-MT halt case (ie. infinite loop) the CPU is doing nothing  in cps_cleanup_dead_cpu()
637 		 * Wait for the core to enter a powered down or clock gated  in cps_cleanup_dead_cpu()
657 			 * The core ought to have powered down, but didn't &  in cps_cleanup_dead_cpu()
660 			 * 1 & it powered back up as soon as we powered it  in cps_cleanup_dead_cpu()
668 				 "CPU%u hasn't powered down, seq. state %u\n",  in cps_cleanup_dead_cpu()
673 		/* Indicate the core is powered off */  in cps_cleanup_dead_cpu()
724 		return -ENODEV;  in register_cps_smp_ops()
727 	/* check we have a GIC - we need one for IPIs */  in register_cps_smp_ops()
730 		return -ENODEV;  in register_cps_smp_ops()