186 static void cps_gen_cache_routine(u32 **pp, struct uasm_label **pl,  in cps_gen_cache_routine()  argument
200 	UASM_i_LA(pp, GPR_T0, (long)CKSEG0);  in cps_gen_cache_routine()
204 		uasm_i_addiu(pp, GPR_T1, GPR_T0, cache_size);  in cps_gen_cache_routine()
206 		UASM_i_LA(pp, GPR_T1, (long)(CKSEG0 + cache_size));  in cps_gen_cache_routine()
209 	uasm_build_label(pl, *pp, lbl);  in cps_gen_cache_routine()
214 			uasm_i_cache(pp, op, 0, GPR_T0);  in cps_gen_cache_routine()
215 			uasm_i_addiu(pp, GPR_T0, GPR_T0, cache->linesz);  in cps_gen_cache_routine()
217 			uasm_i_cache(pp, op, i * cache->linesz, GPR_T0);  in cps_gen_cache_routine()
223 		uasm_i_addiu(pp, GPR_T0, GPR_T0, unroll_lines * cache->linesz);  in cps_gen_cache_routine()
226 	uasm_il_bne(pp, pr, GPR_T0, GPR_T1, lbl);  in cps_gen_cache_routine()
227 	uasm_i_nop(pp);  in cps_gen_cache_routine()
230 static int cps_gen_flush_fsb(u32 **pp, struct uasm_label **pl,  in cps_gen_flush_fsb()  argument
272 	uasm_i_mfc0(pp, GPR_T2, 25, (perf_counter * 2) + 0); /* PerfCtlN */  in cps_gen_flush_fsb()
273 	uasm_i_mfc0(pp, GPR_T3, 25, (perf_counter * 2) + 1); /* PerfCntN */  in cps_gen_flush_fsb()
276 	uasm_i_addiu(pp, GPR_T0, GPR_ZERO, (perf_event << 5) | 0xf);  in cps_gen_flush_fsb()
277 	uasm_i_mtc0(pp, GPR_T0, 25, (perf_counter * 2) + 0); /* PerfCtlN */  in cps_gen_flush_fsb()
278 	uasm_i_ehb(pp);  in cps_gen_flush_fsb()
279 	uasm_i_mtc0(pp, GPR_ZERO, 25, (perf_counter * 2) + 1); /* PerfCntN */  in cps_gen_flush_fsb()
280 	uasm_i_ehb(pp);  in cps_gen_flush_fsb()
283 	UASM_i_LA(pp, GPR_T0, (long)CKSEG0);  in cps_gen_flush_fsb()
286 	uasm_build_label(pl, *pp, lbl);  in cps_gen_flush_fsb()
290 		uasm_i_lw(pp, GPR_ZERO, i * line_size * line_stride, GPR_T0);  in cps_gen_flush_fsb()
297 		uasm_i_cache(pp, Hit_Invalidate_D,  in cps_gen_flush_fsb()
299 		uasm_i_cache(pp, Hit_Writeback_Inv_SD,  in cps_gen_flush_fsb()
304 	uasm_i_sync(pp, __SYNC_full);  in cps_gen_flush_fsb()
305 	uasm_i_ehb(pp);  in cps_gen_flush_fsb()
308 	uasm_i_mfc0(pp, GPR_T1, 25, (perf_counter * 2) + 1); /* PerfCntN */  in cps_gen_flush_fsb()
311 	uasm_il_beqz(pp, pr, GPR_T1, lbl);  in cps_gen_flush_fsb()
312 	uasm_i_nop(pp);  in cps_gen_flush_fsb()
315 	uasm_i_mtc0(pp, GPR_T2, 25, (perf_counter * 2) + 0); /* PerfCtlN */  in cps_gen_flush_fsb()
316 	uasm_i_ehb(pp);  in cps_gen_flush_fsb()
317 	uasm_i_mtc0(pp, GPR_T3, 25, (perf_counter * 2) + 1); /* PerfCntN */  in cps_gen_flush_fsb()
318 	uasm_i_ehb(pp);  in cps_gen_flush_fsb()
323 static void cps_gen_set_top_bit(u32 **pp, struct uasm_label **pl,  in cps_gen_set_top_bit()  argument
327 	uasm_i_lui(pp, GPR_T0, uasm_rel_hi(0x80000000));  in cps_gen_set_top_bit()
328 	uasm_build_label(pl, *pp, lbl);  in cps_gen_set_top_bit()
329 	uasm_i_ll(pp, GPR_T1, 0, r_addr);  in cps_gen_set_top_bit()
330 	uasm_i_or(pp, GPR_T1, GPR_T1, GPR_T0);  in cps_gen_set_top_bit()
331 	uasm_i_sc(pp, GPR_T1, 0, r_addr);  in cps_gen_set_top_bit()
332 	uasm_il_beqz(pp, pr, GPR_T1, lbl);  in cps_gen_set_top_bit()
333 	uasm_i_nop(pp);  in cps_gen_set_top_bit()