61 	#define CNTR_EVEN	0x55555555  macro
939 	[PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, P },
940 	[PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },
941 	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x02, CNTR_EVEN, T },
948 	[PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, P },
949 	[PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },
950 	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x27, CNTR_EVEN, T },
955 	[PERF_COUNT_HW_CPU_CYCLES]          = { 0x00, CNTR_EVEN | CNTR_ODD },
956 	[PERF_COUNT_HW_INSTRUCTIONS]        = { 0x01, CNTR_EVEN | CNTR_ODD },
958 	[PERF_COUNT_HW_CACHE_REFERENCES]    = { 0x45, CNTR_EVEN | CNTR_ODD },
959 	[PERF_COUNT_HW_CACHE_MISSES]        = { 0x48, CNTR_EVEN | CNTR_ODD },
960 	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x15, CNTR_EVEN | CNTR_ODD },
961 	[PERF_COUNT_HW_BRANCH_MISSES]       = { 0x16, CNTR_EVEN | CNTR_ODD },
965 	[PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN },
967 	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x01, CNTR_EVEN },
1000 	[PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, T },
1001 	[PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },
1018 		[C(RESULT_ACCESS)]	= { 0x0a, CNTR_EVEN, T },
1019 		[C(RESULT_MISS)]	= { 0x0b, CNTR_EVEN | CNTR_ODD, T },
1022 		[C(RESULT_ACCESS)]	= { 0x0a, CNTR_EVEN, T },
1023 		[C(RESULT_MISS)]	= { 0x0b, CNTR_EVEN | CNTR_ODD, T },
1028 		[C(RESULT_ACCESS)]	= { 0x09, CNTR_EVEN, T },
1032 		[C(RESULT_ACCESS)]	= { 0x09, CNTR_EVEN, T },
1036 		[C(RESULT_ACCESS)]	= { 0x14, CNTR_EVEN, T },
1046 		[C(RESULT_MISS)]	= { 0x16, CNTR_EVEN, P },
1050 		[C(RESULT_MISS)]	= { 0x16, CNTR_EVEN, P },
1055 		[C(RESULT_ACCESS)]	= { 0x06, CNTR_EVEN, T },
1059 		[C(RESULT_ACCESS)]	= { 0x06, CNTR_EVEN, T },
1065 		[C(RESULT_ACCESS)]	= { 0x05, CNTR_EVEN, T },
1069 		[C(RESULT_ACCESS)]	= { 0x05, CNTR_EVEN, T },
1076 		[C(RESULT_ACCESS)]	= { 0x02, CNTR_EVEN, T },
1080 		[C(RESULT_ACCESS)]	= { 0x02, CNTR_EVEN, T },
1109 		[C(RESULT_ACCESS)]	= { 0x06, CNTR_EVEN, T },
1113 		[C(RESULT_ACCESS)]	= { 0x06, CNTR_EVEN, T },
1117 		[C(RESULT_ACCESS)]	= { 0x34, CNTR_EVEN, T },
1127 		[C(RESULT_MISS)]	= { 0x1d, CNTR_EVEN, P },
1131 		[C(RESULT_MISS)]	= { 0x1d, CNTR_EVEN, P },
1141 		[C(RESULT_ACCESS)]	= { 0x04, CNTR_EVEN, T },
1145 		[C(RESULT_ACCESS)]	= { 0x04, CNTR_EVEN, T },
1152 		[C(RESULT_ACCESS)]	= { 0x27, CNTR_EVEN, T },
1156 		[C(RESULT_ACCESS)]	= { 0x27, CNTR_EVEN, T },
1168 		[C(RESULT_ACCESS)]	= { 0x46, CNTR_EVEN | CNTR_ODD },
1169 		[C(RESULT_MISS)]	= { 0x49, CNTR_EVEN | CNTR_ODD },
1172 		[C(RESULT_ACCESS)]	= { 0x47, CNTR_EVEN | CNTR_ODD },
1173 		[C(RESULT_MISS)]	= { 0x4a, CNTR_EVEN | CNTR_ODD },
1178 		[C(RESULT_ACCESS)]	= { 0x84, CNTR_EVEN | CNTR_ODD },
1179 		[C(RESULT_MISS)]	= { 0x85, CNTR_EVEN | CNTR_ODD },
1185 		[C(RESULT_ACCESS)]	= { 0x40, CNTR_EVEN | CNTR_ODD },
1186 		[C(RESULT_MISS)]	= { 0x41, CNTR_EVEN | CNTR_ODD },
1189 		[C(RESULT_ACCESS)]	= { 0x40, CNTR_EVEN | CNTR_ODD },
1190 		[C(RESULT_MISS)]	= { 0x41, CNTR_EVEN | CNTR_ODD },
1196 		[C(RESULT_ACCESS)]	= { 0x15, CNTR_EVEN | CNTR_ODD },
1197 		[C(RESULT_MISS)]	= { 0x16, CNTR_EVEN | CNTR_ODD },
1222 		[C(RESULT_MISS)]        = { 0x04, CNTR_EVEN },
1225 		[C(RESULT_MISS)]        = { 0x04, CNTR_EVEN },
1247 		[C(RESULT_ACCESS)]      = { 0x01, CNTR_EVEN },
1251 		[C(RESULT_ACCESS)]      = { 0x01, CNTR_EVEN },
1385 		[C(RESULT_ACCESS)]	= { 12, CNTR_EVEN, T },
1389 		[C(RESULT_ACCESS)]	= { 12, CNTR_EVEN, T },
1395 		[C(RESULT_ACCESS)]	= { 10, CNTR_EVEN, T },
1399 		[C(RESULT_ACCESS)]	= { 10, CNTR_EVEN, T },
1403 		[C(RESULT_ACCESS)]	= { 23, CNTR_EVEN, T },
1412 		[C(RESULT_ACCESS)]	= { 28, CNTR_EVEN, P },
1416 		[C(RESULT_ACCESS)]	= { 28, CNTR_EVEN, P },
1714 			raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;  in mipsxx_pmu_map_raw_event()
1717 				raw_id > 127 ? CNTR_ODD : CNTR_EVEN;  in mipsxx_pmu_map_raw_event()
1728 			raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;  in mipsxx_pmu_map_raw_event()
1731 				raw_id > 127 ? CNTR_ODD : CNTR_EVEN;  in mipsxx_pmu_map_raw_event()
1744 			raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;  in mipsxx_pmu_map_raw_event()
1747 				raw_id > 127 ? CNTR_ODD : CNTR_EVEN;  in mipsxx_pmu_map_raw_event()
1754 			raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;  in mipsxx_pmu_map_raw_event()
1757 				raw_id > 127 ? CNTR_ODD : CNTR_EVEN;  in mipsxx_pmu_map_raw_event()
1768 			raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;  in mipsxx_pmu_map_raw_event()
1771 				raw_id > 255 ? CNTR_ODD : CNTR_EVEN;  in mipsxx_pmu_map_raw_event()
1780 		raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;  in mipsxx_pmu_map_raw_event()
1784 			raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;  in mipsxx_pmu_map_raw_event()
1787 				raw_id > 127 ? CNTR_ODD : CNTR_EVEN;  in mipsxx_pmu_map_raw_event()
1799 			raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;  in mipsxx_pmu_map_raw_event()
1802 				raw_id > 127 ? CNTR_ODD : CNTR_EVEN;  in mipsxx_pmu_map_raw_event()
1814 			raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;  in mipsxx_pmu_map_raw_event()
1817 				raw_id > 127 ? CNTR_ODD : CNTR_EVEN;  in mipsxx_pmu_map_raw_event()
1825 				raw_id > 127 ? CNTR_ODD : CNTR_EVEN;  in mipsxx_pmu_map_raw_event()