Lines Matching refs:C
5 * Copyright (C) 2010 MIPS Technologies, Inc.
6 * Copyright (C) 2011 Cavium Networks, Inc.
74 #define C(x) PERF_COUNT_HW_CACHE_##x
1009 [C(L1D)] = {
1016 [C(OP_READ)] = {
1017 [C(RESULT_ACCESS)] = { 0x0a, CNTR_EVEN, T },
1018 [C(RESULT_MISS)] = { 0x0b, CNTR_EVEN | CNTR_ODD, T },
1020 [C(OP_WRITE)] = {
1021 [C(RESULT_ACCESS)] = { 0x0a, CNTR_EVEN, T },
1022 [C(RESULT_MISS)] = { 0x0b, CNTR_EVEN | CNTR_ODD, T },
1025 [C(L1I)] = {
1026 [C(OP_READ)] = {
1027 [C(RESULT_ACCESS)] = { 0x09, CNTR_EVEN, T },
1028 [C(RESULT_MISS)] = { 0x09, CNTR_ODD, T },
1030 [C(OP_WRITE)] = {
1031 [C(RESULT_ACCESS)] = { 0x09, CNTR_EVEN, T },
1032 [C(RESULT_MISS)] = { 0x09, CNTR_ODD, T },
1034 [C(OP_PREFETCH)] = {
1035 [C(RESULT_ACCESS)] = { 0x14, CNTR_EVEN, T },
1042 [C(LL)] = {
1043 [C(OP_READ)] = {
1044 [C(RESULT_ACCESS)] = { 0x15, CNTR_ODD, P },
1045 [C(RESULT_MISS)] = { 0x16, CNTR_EVEN, P },
1047 [C(OP_WRITE)] = {
1048 [C(RESULT_ACCESS)] = { 0x15, CNTR_ODD, P },
1049 [C(RESULT_MISS)] = { 0x16, CNTR_EVEN, P },
1052 [C(DTLB)] = {
1053 [C(OP_READ)] = {
1054 [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T },
1055 [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T },
1057 [C(OP_WRITE)] = {
1058 [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T },
1059 [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T },
1062 [C(ITLB)] = {
1063 [C(OP_READ)] = {
1064 [C(RESULT_ACCESS)] = { 0x05, CNTR_EVEN, T },
1065 [C(RESULT_MISS)] = { 0x05, CNTR_ODD, T },
1067 [C(OP_WRITE)] = {
1068 [C(RESULT_ACCESS)] = { 0x05, CNTR_EVEN, T },
1069 [C(RESULT_MISS)] = { 0x05, CNTR_ODD, T },
1072 [C(BPU)] = {
1074 [C(OP_READ)] = {
1075 [C(RESULT_ACCESS)] = { 0x02, CNTR_EVEN, T },
1076 [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T },
1078 [C(OP_WRITE)] = {
1079 [C(RESULT_ACCESS)] = { 0x02, CNTR_EVEN, T },
1080 [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T },
1090 [C(L1D)] = {
1097 [C(OP_READ)] = {
1098 [C(RESULT_ACCESS)] = { 0x17, CNTR_ODD, T },
1099 [C(RESULT_MISS)] = { 0x18, CNTR_ODD, T },
1101 [C(OP_WRITE)] = {
1102 [C(RESULT_ACCESS)] = { 0x17, CNTR_ODD, T },
1103 [C(RESULT_MISS)] = { 0x18, CNTR_ODD, T },
1106 [C(L1I)] = {
1107 [C(OP_READ)] = {
1108 [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T },
1109 [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T },
1111 [C(OP_WRITE)] = {
1112 [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T },
1113 [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T },
1115 [C(OP_PREFETCH)] = {
1116 [C(RESULT_ACCESS)] = { 0x34, CNTR_EVEN, T },
1123 [C(LL)] = {
1124 [C(OP_READ)] = {
1125 [C(RESULT_ACCESS)] = { 0x1c, CNTR_ODD, P },
1126 [C(RESULT_MISS)] = { 0x1d, CNTR_EVEN, P },
1128 [C(OP_WRITE)] = {
1129 [C(RESULT_ACCESS)] = { 0x1c, CNTR_ODD, P },
1130 [C(RESULT_MISS)] = { 0x1d, CNTR_EVEN, P },
1138 [C(ITLB)] = {
1139 [C(OP_READ)] = {
1140 [C(RESULT_ACCESS)] = { 0x04, CNTR_EVEN, T },
1141 [C(RESULT_MISS)] = { 0x04, CNTR_ODD, T },
1143 [C(OP_WRITE)] = {
1144 [C(RESULT_ACCESS)] = { 0x04, CNTR_EVEN, T },
1145 [C(RESULT_MISS)] = { 0x04, CNTR_ODD, T },
1148 [C(BPU)] = {
1150 [C(OP_READ)] = {
1151 [C(RESULT_ACCESS)] = { 0x27, CNTR_EVEN, T },
1152 [C(RESULT_MISS)] = { 0x27, CNTR_ODD, T },
1154 [C(OP_WRITE)] = {
1155 [C(RESULT_ACCESS)] = { 0x27, CNTR_EVEN, T },
1156 [C(RESULT_MISS)] = { 0x27, CNTR_ODD, T },
1165 [C(L1D)] = {
1166 [C(OP_READ)] = {
1167 [C(RESULT_ACCESS)] = { 0x46, CNTR_EVEN | CNTR_ODD },
1168 [C(RESULT_MISS)] = { 0x49, CNTR_EVEN | CNTR_ODD },
1170 [C(OP_WRITE)] = {
1171 [C(RESULT_ACCESS)] = { 0x47, CNTR_EVEN | CNTR_ODD },
1172 [C(RESULT_MISS)] = { 0x4a, CNTR_EVEN | CNTR_ODD },
1175 [C(L1I)] = {
1176 [C(OP_READ)] = {
1177 [C(RESULT_ACCESS)] = { 0x84, CNTR_EVEN | CNTR_ODD },
1178 [C(RESULT_MISS)] = { 0x85, CNTR_EVEN | CNTR_ODD },
1181 [C(DTLB)] = {
1183 [C(OP_READ)] = {
1184 [C(RESULT_ACCESS)] = { 0x40, CNTR_EVEN | CNTR_ODD },
1185 [C(RESULT_MISS)] = { 0x41, CNTR_EVEN | CNTR_ODD },
1187 [C(OP_WRITE)] = {
1188 [C(RESULT_ACCESS)] = { 0x40, CNTR_EVEN | CNTR_ODD },
1189 [C(RESULT_MISS)] = { 0x41, CNTR_EVEN | CNTR_ODD },
1192 [C(BPU)] = {
1194 [C(OP_READ)] = {
1195 [C(RESULT_ACCESS)] = { 0x15, CNTR_EVEN | CNTR_ODD },
1196 [C(RESULT_MISS)] = { 0x16, CNTR_EVEN | CNTR_ODD },
1205 [C(L1D)] = {
1212 [C(OP_READ)] = {
1213 [C(RESULT_MISS)] = { 0x04, CNTR_ODD },
1215 [C(OP_WRITE)] = {
1216 [C(RESULT_MISS)] = { 0x04, CNTR_ODD },
1219 [C(L1I)] = {
1220 [C(OP_READ)] = {
1221 [C(RESULT_MISS)] = { 0x04, CNTR_EVEN },
1223 [C(OP_WRITE)] = {
1224 [C(RESULT_MISS)] = { 0x04, CNTR_EVEN },
1227 [C(DTLB)] = {
1228 [C(OP_READ)] = {
1229 [C(RESULT_MISS)] = { 0x09, CNTR_ODD },
1231 [C(OP_WRITE)] = {
1232 [C(RESULT_MISS)] = { 0x09, CNTR_ODD },
1235 [C(ITLB)] = {
1236 [C(OP_READ)] = {
1237 [C(RESULT_MISS)] = { 0x0c, CNTR_ODD },
1239 [C(OP_WRITE)] = {
1240 [C(RESULT_MISS)] = { 0x0c, CNTR_ODD },
1243 [C(BPU)] = {
1245 [C(OP_READ)] = {
1246 [C(RESULT_ACCESS)] = { 0x01, CNTR_EVEN },
1247 [C(RESULT_MISS)] = { 0x01, CNTR_ODD },
1249 [C(OP_WRITE)] = {
1250 [C(RESULT_ACCESS)] = { 0x01, CNTR_EVEN },
1251 [C(RESULT_MISS)] = { 0x01, CNTR_ODD },
1260 [C(L1D)] = {
1267 [C(OP_READ)] = {
1268 [C(RESULT_ACCESS)] = { 0x156, CNTR_ALL },
1270 [C(OP_WRITE)] = {
1271 [C(RESULT_ACCESS)] = { 0x155, CNTR_ALL },
1272 [C(RESULT_MISS)] = { 0x153, CNTR_ALL },
1275 [C(L1I)] = {
1276 [C(OP_READ)] = {
1277 [C(RESULT_MISS)] = { 0x18, CNTR_ALL },
1279 [C(OP_WRITE)] = {
1280 [C(RESULT_MISS)] = { 0x18, CNTR_ALL },
1283 [C(LL)] = {
1284 [C(OP_READ)] = {
1285 [C(RESULT_ACCESS)] = { 0x1b6, CNTR_ALL },
1287 [C(OP_WRITE)] = {
1288 [C(RESULT_ACCESS)] = { 0x1b7, CNTR_ALL },
1290 [C(OP_PREFETCH)] = {
1291 [C(RESULT_ACCESS)] = { 0x1bf, CNTR_ALL },
1294 [C(DTLB)] = {
1295 [C(OP_READ)] = {
1296 [C(RESULT_MISS)] = { 0x92, CNTR_ALL },
1298 [C(OP_WRITE)] = {
1299 [C(RESULT_MISS)] = { 0x92, CNTR_ALL },
1302 [C(ITLB)] = {
1303 [C(OP_READ)] = {
1304 [C(RESULT_MISS)] = { 0x1a, CNTR_ALL },
1306 [C(OP_WRITE)] = {
1307 [C(RESULT_MISS)] = { 0x1a, CNTR_ALL },
1310 [C(BPU)] = {
1312 [C(OP_READ)] = {
1313 [C(RESULT_ACCESS)] = { 0x94, CNTR_ALL },
1314 [C(RESULT_MISS)] = { 0x9c, CNTR_ALL },
1323 [C(L1D)] = {
1330 [C(OP_READ)] = {
1331 [C(RESULT_ACCESS)] = { 0x1e, CNTR_ALL },
1332 [C(RESULT_MISS)] = { 0x1f, CNTR_ALL },
1334 [C(OP_PREFETCH)] = {
1335 [C(RESULT_ACCESS)] = { 0xaa, CNTR_ALL },
1336 [C(RESULT_MISS)] = { 0xa9, CNTR_ALL },
1339 [C(L1I)] = {
1340 [C(OP_READ)] = {
1341 [C(RESULT_ACCESS)] = { 0x1c, CNTR_ALL },
1342 [C(RESULT_MISS)] = { 0x1d, CNTR_ALL },
1345 [C(LL)] = {
1346 [C(OP_READ)] = {
1347 [C(RESULT_ACCESS)] = { 0x2e, CNTR_ALL },
1348 [C(RESULT_MISS)] = { 0x2f, CNTR_ALL },
1351 [C(DTLB)] = {
1352 [C(OP_READ)] = {
1353 [C(RESULT_ACCESS)] = { 0x14, CNTR_ALL },
1354 [C(RESULT_MISS)] = { 0x1b, CNTR_ALL },
1357 [C(ITLB)] = {
1358 [C(OP_READ)] = {
1359 [C(RESULT_MISS)] = { 0x1a, CNTR_ALL },
1362 [C(BPU)] = {
1364 [C(OP_READ)] = {
1365 [C(RESULT_ACCESS)] = { 0x02, CNTR_ALL },
1366 [C(RESULT_MISS)] = { 0x08, CNTR_ALL },
1376 [C(L1D)] = {
1383 [C(OP_READ)] = {
1384 [C(RESULT_ACCESS)] = { 12, CNTR_EVEN, T },
1385 [C(RESULT_MISS)] = { 12, CNTR_ODD, T },
1387 [C(OP_WRITE)] = {
1388 [C(RESULT_ACCESS)] = { 12, CNTR_EVEN, T },
1389 [C(RESULT_MISS)] = { 12, CNTR_ODD, T },
1392 [C(L1I)] = {
1393 [C(OP_READ)] = {
1394 [C(RESULT_ACCESS)] = { 10, CNTR_EVEN, T },
1395 [C(RESULT_MISS)] = { 10, CNTR_ODD, T },
1397 [C(OP_WRITE)] = {
1398 [C(RESULT_ACCESS)] = { 10, CNTR_EVEN, T },
1399 [C(RESULT_MISS)] = { 10, CNTR_ODD, T },
1401 [C(OP_PREFETCH)] = {
1402 [C(RESULT_ACCESS)] = { 23, CNTR_EVEN, T },
1409 [C(LL)] = {
1410 [C(OP_READ)] = {
1411 [C(RESULT_ACCESS)] = { 28, CNTR_EVEN, P },
1412 [C(RESULT_MISS)] = { 28, CNTR_ODD, P },
1414 [C(OP_WRITE)] = {
1415 [C(RESULT_ACCESS)] = { 28, CNTR_EVEN, P },
1416 [C(RESULT_MISS)] = { 28, CNTR_ODD, P },
1419 [C(BPU)] = {
1421 [C(OP_READ)] = {
1422 [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T },
1424 [C(OP_WRITE)] = {
1425 [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T },
1434 [C(L1D)] = {
1435 [C(OP_READ)] = {
1436 [C(RESULT_ACCESS)] = { 0x2b, CNTR_ALL },
1437 [C(RESULT_MISS)] = { 0x2e, CNTR_ALL },
1439 [C(OP_WRITE)] = {
1440 [C(RESULT_ACCESS)] = { 0x30, CNTR_ALL },
1443 [C(L1I)] = {
1444 [C(OP_READ)] = {
1445 [C(RESULT_ACCESS)] = { 0x18, CNTR_ALL },
1447 [C(OP_PREFETCH)] = {
1448 [C(RESULT_ACCESS)] = { 0x19, CNTR_ALL },
1451 [C(DTLB)] = {
1456 [C(OP_READ)] = {
1457 [C(RESULT_MISS)] = { 0x35, CNTR_ALL },
1459 [C(OP_WRITE)] = {
1460 [C(RESULT_MISS)] = { 0x35, CNTR_ALL },
1463 [C(ITLB)] = {
1464 [C(OP_READ)] = {
1465 [C(RESULT_MISS)] = { 0x37, CNTR_ALL },