Lines Matching +full:- +full:c
1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) xxxx the Anonymous
6 * Copyright (C) 1994 - 2006 Ralf Baechle
7 * Copyright (C) 2003, 2004 Maciej W. Rozycki
8 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
20 #include <asm/cpu-features.h>
21 #include <asm/cpu-type.h>
28 #include <asm/pgtable-bits.h>
33 #include "fpu-probe.h"
35 #include <asm/mach-loongson64/cpucfg-emul.h>
90 static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags);
134 cpu_data[0].tlbsize -= cpu_data[0].tlbsizeftlbways * in ftlb_disable()
147 static inline void cpu_set_mt_per_tc_perf(struct cpuinfo_mips *c) in cpu_set_mt_per_tc_perf() argument
150 c->options |= MIPS_CPU_MT_PER_TC_PERF_COUNTERS; in cpu_set_mt_per_tc_perf()
155 struct cpuinfo_mips *c = ¤t_cpu_data; in check_errata() local
164 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2) in check_errata()
211 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c) in cpu_probe_vmbits() argument
216 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL); in cpu_probe_vmbits()
220 static void set_isa(struct cpuinfo_mips *c, unsigned int isa) in set_isa() argument
224 c->isa_level |= MIPS_CPU_ISA_M32R5 | MIPS_CPU_ISA_M64R5; in set_isa()
228 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2; in set_isa()
232 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1; in set_isa()
236 c->isa_level |= MIPS_CPU_ISA_V; in set_isa()
240 c->isa_level |= MIPS_CPU_ISA_IV; in set_isa()
244 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III; in set_isa()
250 c->isa_level |= MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6; in set_isa()
254 c->isa_level |= MIPS_CPU_ISA_M32R6; in set_isa()
259 c->isa_level |= MIPS_CPU_ISA_M32R5; in set_isa()
263 c->isa_level |= MIPS_CPU_ISA_M32R2; in set_isa()
267 c->isa_level |= MIPS_CPU_ISA_M32R1; in set_isa()
271 c->isa_level |= MIPS_CPU_ISA_II; in set_isa()
280 static unsigned int calculate_ftlb_probability(struct cpuinfo_mips *c) in calculate_ftlb_probability() argument
283 unsigned int probability = c->tlbsize / c->tlbsizevtlb; in calculate_ftlb_probability()
306 static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags) in set_ftlb_enable() argument
311 switch (c->cputype) { in set_ftlb_enable()
325 config |= calculate_ftlb_probability(c) in set_ftlb_enable()
342 /* Loongson-3 cores use Config6 to enable the FTLB */ in set_ftlb_enable()
358 static int mm_config(struct cpuinfo_mips *c) in mm_config() argument
366 * It's implementation dependent what type of write-merge is supported in mm_config()
369 * write-through caching unsupported. In this case just ignore the in mm_config()
372 switch (c->cputype) { in mm_config()
378 c->options |= MIPS_CPU_MM_FULL; in mm_config()
396 c->options |= MIPS_CPU_MM_SYSAD; in mm_config()
398 c->options |= MIPS_CPU_MM_FULL; in mm_config()
404 static inline unsigned int decode_config0(struct cpuinfo_mips *c) in decode_config0() argument
416 c->options |= MIPS_CPU_TLB; in decode_config0()
418 c->options |= MIPS_CPU_TLB | MIPS_CPU_FTLB; in decode_config0()
425 set_isa(c, MIPS_CPU_ISA_M32R1); in decode_config0()
428 set_isa(c, MIPS_CPU_ISA_M32R2); in decode_config0()
431 set_isa(c, MIPS_CPU_ISA_M32R6); in decode_config0()
440 set_isa(c, MIPS_CPU_ISA_M64R1); in decode_config0()
443 set_isa(c, MIPS_CPU_ISA_M64R2); in decode_config0()
446 set_isa(c, MIPS_CPU_ISA_M64R6); in decode_config0()
462 static inline unsigned int decode_config1(struct cpuinfo_mips *c) in decode_config1() argument
469 c->ases |= MIPS_ASE_MDMX; in decode_config1()
471 c->options |= MIPS_CPU_PERF; in decode_config1()
473 c->options |= MIPS_CPU_WATCH; in decode_config1()
475 c->ases |= MIPS_ASE_MIPS16; in decode_config1()
477 c->options |= MIPS_CPU_EJTAG; in decode_config1()
479 c->options |= MIPS_CPU_FPU; in decode_config1()
480 c->options |= MIPS_CPU_32FPR; in decode_config1()
483 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1; in decode_config1()
484 c->tlbsizevtlb = c->tlbsize; in decode_config1()
485 c->tlbsizeftlbsets = 0; in decode_config1()
491 static inline unsigned int decode_config2(struct cpuinfo_mips *c) in decode_config2() argument
498 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT; in decode_config2()
503 static inline unsigned int decode_config3(struct cpuinfo_mips *c) in decode_config3() argument
510 c->ases |= MIPS_ASE_SMARTMIPS; in decode_config3()
511 c->options |= MIPS_CPU_RIXI | MIPS_CPU_CTXTC; in decode_config3()
514 c->options |= MIPS_CPU_RIXI; in decode_config3()
516 c->options |= MIPS_CPU_CTXTC; in decode_config3()
518 c->ases |= MIPS_ASE_DSP; in decode_config3()
520 c->ases |= MIPS_ASE_DSP2P; in decode_config3()
522 c->ases |= MIPS_ASE_DSP3; in decode_config3()
525 c->options |= MIPS_CPU_VINT; in decode_config3()
527 c->options |= MIPS_CPU_VEIC; in decode_config3()
529 c->options |= MIPS_CPU_LPA; in decode_config3()
531 c->ases |= MIPS_ASE_MIPSMT; in decode_config3()
533 c->options |= MIPS_CPU_ULRI; in decode_config3()
535 c->options |= MIPS_CPU_MICROMIPS; in decode_config3()
537 c->ases |= MIPS_ASE_VZ; in decode_config3()
539 c->options |= MIPS_CPU_SEGMENTS; in decode_config3()
541 c->options |= MIPS_CPU_BADINSTR; in decode_config3()
543 c->options |= MIPS_CPU_BADINSTRP; in decode_config3()
545 c->ases |= MIPS_ASE_MSA; in decode_config3()
547 c->htw_seq = 0; in decode_config3()
548 c->options |= MIPS_CPU_HTW; in decode_config3()
551 c->options |= MIPS_CPU_CDMM; in decode_config3()
553 c->options |= MIPS_CPU_SP; in decode_config3()
558 static inline unsigned int decode_config4(struct cpuinfo_mips *c) in decode_config4() argument
570 c->options |= MIPS_CPU_TLBINV; in decode_config4()
586 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40; in decode_config4()
587 c->tlbsizevtlb = c->tlbsize; in decode_config4()
590 c->tlbsizevtlb += in decode_config4()
593 c->tlbsize = c->tlbsizevtlb; in decode_config4()
609 set_ftlb_enable(c, 0); in decode_config4()
613 c->tlbsizeftlbsets = 1 << in decode_config4()
616 c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >> in decode_config4()
618 c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets; in decode_config4()
624 c->kscratch_mask = (config4 & MIPS_CONF4_KSCREXIST) in decode_config4()
630 set_cpu_asid_mask(c, asid_mask); in decode_config4()
637 WARN_ON(asid_mask != cpu_asid_mask(c)); in decode_config4()
642 static inline unsigned int decode_config5(struct cpuinfo_mips *c) in decode_config5() argument
660 c->options |= MIPS_CPU_EVA; in decode_config5()
662 c->options |= MIPS_CPU_MAAR; in decode_config5()
664 c->options |= MIPS_CPU_RW_LLB; in decode_config5()
666 c->options |= MIPS_CPU_MVH; in decode_config5()
668 c->options |= MIPS_CPU_VP; in decode_config5()
670 c->ases |= MIPS_ASE_MIPS16E2; in decode_config5()
682 c->options |= MIPS_CPU_MMID; in decode_config5()
703 * bitmap - that's too big in most cases. in decode_config5()
709 if (asid_mask > GENMASK(max_mmid_width - 1, 0)) { in decode_config5()
712 asid_mask = GENMASK(max_mmid_width - 1, 0); in decode_config5()
714 set_cpu_asid_mask(c, asid_mask); in decode_config5()
721 static void decode_configs(struct cpuinfo_mips *c) in decode_configs() argument
726 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER | in decode_configs()
729 c->scache.flags = MIPS_CACHE_NOT_PRESENT; in decode_configs()
732 set_ftlb_enable(c, mips_ftlb_disabled ? 0 : FTLB_EN); in decode_configs()
734 ok = decode_config0(c); /* Read Config registers. */ in decode_configs()
737 ok = decode_config1(c); in decode_configs()
739 ok = decode_config2(c); in decode_configs()
741 ok = decode_config3(c); in decode_configs()
743 ok = decode_config4(c); in decode_configs()
745 ok = decode_config5(c); in decode_configs()
757 c->options |= MIPS_CPU_EBASE_WG; in decode_configs()
764 * On pre-r6 cores, this may well clobber the upper bits in decode_configs()
766 * hitting UNDEFINED dm*c0 behaviour if EBase is 32-bit. in decode_configs()
776 c->options |= MIPS_CPU_EBASE_WG; in decode_configs()
783 set_ftlb_enable(c, (mips_ftlb_disabled ? 0 : FTLB_EN) | FTLB_SET_PROB); in decode_configs()
785 mips_probe_watch_registers(c); in decode_configs()
793 core >>= fls(core_nvpes()) - 1; in decode_configs()
794 cpu_set_core(c, core); in decode_configs()
827 static inline unsigned int decode_guest_config0(struct cpuinfo_mips *c) in decode_guest_config0() argument
834 c->guest.conf |= BIT(1); in decode_guest_config0()
838 static inline unsigned int decode_guest_config1(struct cpuinfo_mips *c) in decode_guest_config1() argument
847 c->guest.options |= MIPS_CPU_FPU; in decode_guest_config1()
849 c->guest.options_dyn |= MIPS_CPU_FPU; in decode_guest_config1()
852 c->guest.options |= MIPS_CPU_WATCH; in decode_guest_config1()
854 c->guest.options_dyn |= MIPS_CPU_WATCH; in decode_guest_config1()
857 c->guest.options |= MIPS_CPU_PERF; in decode_guest_config1()
859 c->guest.options_dyn |= MIPS_CPU_PERF; in decode_guest_config1()
862 c->guest.conf |= BIT(2); in decode_guest_config1()
866 static inline unsigned int decode_guest_config2(struct cpuinfo_mips *c) in decode_guest_config2() argument
873 c->guest.conf |= BIT(3); in decode_guest_config2()
877 static inline unsigned int decode_guest_config3(struct cpuinfo_mips *c) in decode_guest_config3() argument
886 c->guest.options |= MIPS_CPU_CTXTC; in decode_guest_config3()
888 c->guest.options_dyn |= MIPS_CPU_CTXTC; in decode_guest_config3()
891 c->guest.options |= MIPS_CPU_HTW; in decode_guest_config3()
894 c->guest.options |= MIPS_CPU_ULRI; in decode_guest_config3()
897 c->guest.options |= MIPS_CPU_SEGMENTS; in decode_guest_config3()
900 c->guest.options |= MIPS_CPU_BADINSTR; in decode_guest_config3()
902 c->guest.options |= MIPS_CPU_BADINSTRP; in decode_guest_config3()
905 c->guest.ases |= MIPS_ASE_MSA; in decode_guest_config3()
907 c->guest.ases_dyn |= MIPS_ASE_MSA; in decode_guest_config3()
910 c->guest.conf |= BIT(4); in decode_guest_config3()
914 static inline unsigned int decode_guest_config4(struct cpuinfo_mips *c) in decode_guest_config4() argument
921 c->guest.kscratch_mask = (config4 & MIPS_CONF4_KSCREXIST) in decode_guest_config4()
925 c->guest.conf |= BIT(5); in decode_guest_config4()
929 static inline unsigned int decode_guest_config5(struct cpuinfo_mips *c) in decode_guest_config5() argument
937 c->guest.options |= MIPS_CPU_MAAR; in decode_guest_config5()
939 c->guest.options_dyn |= MIPS_CPU_MAAR; in decode_guest_config5()
942 c->guest.options |= MIPS_CPU_RW_LLB; in decode_guest_config5()
945 c->guest.options |= MIPS_CPU_MVH; in decode_guest_config5()
948 c->guest.conf |= BIT(6); in decode_guest_config5()
952 static inline void decode_guest_configs(struct cpuinfo_mips *c) in decode_guest_configs() argument
956 ok = decode_guest_config0(c); in decode_guest_configs()
958 ok = decode_guest_config1(c); in decode_guest_configs()
960 ok = decode_guest_config2(c); in decode_guest_configs()
962 ok = decode_guest_config3(c); in decode_guest_configs()
964 ok = decode_guest_config4(c); in decode_guest_configs()
966 decode_guest_config5(c); in decode_guest_configs()
969 static inline void cpu_probe_guestctl0(struct cpuinfo_mips *c) in cpu_probe_guestctl0() argument
976 c->options |= MIPS_CPU_GUESTCTL0EXT; in cpu_probe_guestctl0()
978 c->options |= MIPS_CPU_GUESTCTL1; in cpu_probe_guestctl0()
980 c->options |= MIPS_CPU_GUESTCTL2; in cpu_probe_guestctl0()
982 c->options |= MIPS_CPU_GUESTID; in cpu_probe_guestctl0()
998 c->options |= MIPS_CPU_DRG; in cpu_probe_guestctl0()
1003 static inline void cpu_probe_guestctl1(struct cpuinfo_mips *c) in cpu_probe_guestctl1() argument
1009 c->guestid_mask = (read_c0_guestctl1() & MIPS_GCTL1_ID) in cpu_probe_guestctl1()
1015 static inline void cpu_probe_gtoffset(struct cpuinfo_mips *c) in cpu_probe_gtoffset() argument
1020 c->gtoffset_mask = read_c0_gtoffset(); in cpu_probe_gtoffset()
1024 static inline void cpu_probe_vz(struct cpuinfo_mips *c) in cpu_probe_vz() argument
1026 cpu_probe_guestctl0(c); in cpu_probe_vz()
1028 cpu_probe_guestctl1(c); in cpu_probe_vz()
1030 cpu_probe_gtoffset(c); in cpu_probe_vz()
1032 decode_guest_configs(c); in cpu_probe_vz()
1038 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) in cpu_probe_legacy() argument
1040 switch (c->processor_id & PRID_IMP_MASK) { in cpu_probe_legacy()
1042 c->cputype = CPU_R2000; in cpu_probe_legacy()
1044 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS; in cpu_probe_legacy()
1045 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | in cpu_probe_legacy()
1048 c->options |= MIPS_CPU_FPU; in cpu_probe_legacy()
1049 c->tlbsize = 64; in cpu_probe_legacy()
1052 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) { in cpu_probe_legacy()
1054 c->cputype = CPU_R3081E; in cpu_probe_legacy()
1057 c->cputype = CPU_R3000A; in cpu_probe_legacy()
1061 c->cputype = CPU_R3000; in cpu_probe_legacy()
1064 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS; in cpu_probe_legacy()
1065 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | in cpu_probe_legacy()
1068 c->options |= MIPS_CPU_FPU; in cpu_probe_legacy()
1069 c->tlbsize = 64; in cpu_probe_legacy()
1073 if ((c->processor_id & PRID_REV_MASK) >= in cpu_probe_legacy()
1075 c->cputype = CPU_R4400PC; in cpu_probe_legacy()
1078 c->cputype = CPU_R4000PC; in cpu_probe_legacy()
1102 if ((c->processor_id & PRID_REV_MASK) >= in cpu_probe_legacy()
1104 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC; in cpu_probe_legacy()
1107 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC; in cpu_probe_legacy()
1112 set_isa(c, MIPS_CPU_ISA_III); in cpu_probe_legacy()
1113 c->fpu_msk31 |= FPU_CSR_CONDX; in cpu_probe_legacy()
1114 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | in cpu_probe_legacy()
1117 c->tlbsize = 48; in cpu_probe_legacy()
1120 c->cputype = CPU_R4300; in cpu_probe_legacy()
1122 set_isa(c, MIPS_CPU_ISA_III); in cpu_probe_legacy()
1123 c->fpu_msk31 |= FPU_CSR_CONDX; in cpu_probe_legacy()
1124 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | in cpu_probe_legacy()
1126 c->tlbsize = 32; in cpu_probe_legacy()
1129 c->cputype = CPU_R4600; in cpu_probe_legacy()
1131 set_isa(c, MIPS_CPU_ISA_III); in cpu_probe_legacy()
1132 c->fpu_msk31 |= FPU_CSR_CONDX; in cpu_probe_legacy()
1133 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | in cpu_probe_legacy()
1135 c->tlbsize = 48; in cpu_probe_legacy()
1145 c->cputype = CPU_R4650; in cpu_probe_legacy()
1147 set_isa(c, MIPS_CPU_ISA_III); in cpu_probe_legacy()
1148 c->fpu_msk31 |= FPU_CSR_CONDX; in cpu_probe_legacy()
1149 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC; in cpu_probe_legacy()
1150 c->tlbsize = 48; in cpu_probe_legacy()
1154 c->cputype = CPU_R4700; in cpu_probe_legacy()
1156 set_isa(c, MIPS_CPU_ISA_III); in cpu_probe_legacy()
1157 c->fpu_msk31 |= FPU_CSR_CONDX; in cpu_probe_legacy()
1158 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | in cpu_probe_legacy()
1160 c->tlbsize = 48; in cpu_probe_legacy()
1163 c->cputype = CPU_TX49XX; in cpu_probe_legacy()
1165 set_isa(c, MIPS_CPU_ISA_III); in cpu_probe_legacy()
1166 c->fpu_msk31 |= FPU_CSR_CONDX; in cpu_probe_legacy()
1167 c->options = R4K_OPTS | MIPS_CPU_LLSC; in cpu_probe_legacy()
1168 if (!(c->processor_id & 0x08)) in cpu_probe_legacy()
1169 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR; in cpu_probe_legacy()
1170 c->tlbsize = 48; in cpu_probe_legacy()
1173 c->cputype = CPU_R5000; in cpu_probe_legacy()
1175 set_isa(c, MIPS_CPU_ISA_IV); in cpu_probe_legacy()
1176 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | in cpu_probe_legacy()
1178 c->tlbsize = 48; in cpu_probe_legacy()
1181 c->cputype = CPU_R5500; in cpu_probe_legacy()
1183 set_isa(c, MIPS_CPU_ISA_IV); in cpu_probe_legacy()
1184 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | in cpu_probe_legacy()
1186 c->tlbsize = 48; in cpu_probe_legacy()
1189 c->cputype = CPU_NEVADA; in cpu_probe_legacy()
1191 set_isa(c, MIPS_CPU_ISA_IV); in cpu_probe_legacy()
1192 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | in cpu_probe_legacy()
1194 c->tlbsize = 48; in cpu_probe_legacy()
1197 c->cputype = CPU_RM7000; in cpu_probe_legacy()
1199 set_isa(c, MIPS_CPU_ISA_IV); in cpu_probe_legacy()
1200 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | in cpu_probe_legacy()
1210 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48; in cpu_probe_legacy()
1213 c->cputype = CPU_R10000; in cpu_probe_legacy()
1215 set_isa(c, MIPS_CPU_ISA_IV); in cpu_probe_legacy()
1216 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | in cpu_probe_legacy()
1220 c->tlbsize = 64; in cpu_probe_legacy()
1223 c->cputype = CPU_R12000; in cpu_probe_legacy()
1225 set_isa(c, MIPS_CPU_ISA_IV); in cpu_probe_legacy()
1226 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | in cpu_probe_legacy()
1230 c->tlbsize = 64; in cpu_probe_legacy()
1234 if (((c->processor_id >> 4) & 0x0f) > 2) { in cpu_probe_legacy()
1235 c->cputype = CPU_R16000; in cpu_probe_legacy()
1238 c->cputype = CPU_R14000; in cpu_probe_legacy()
1241 set_isa(c, MIPS_CPU_ISA_IV); in cpu_probe_legacy()
1242 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | in cpu_probe_legacy()
1246 c->tlbsize = 64; in cpu_probe_legacy()
1249 case PRID_IMP_LOONGSON_64C: /* Loongson-2/3 */ in cpu_probe_legacy()
1250 switch (c->processor_id & PRID_REV_MASK) { in cpu_probe_legacy()
1252 c->cputype = CPU_LOONGSON2EF; in cpu_probe_legacy()
1253 __cpu_name[cpu] = "ICT Loongson-2"; in cpu_probe_legacy()
1255 set_isa(c, MIPS_CPU_ISA_III); in cpu_probe_legacy()
1256 c->fpu_msk31 |= FPU_CSR_CONDX; in cpu_probe_legacy()
1259 c->cputype = CPU_LOONGSON2EF; in cpu_probe_legacy()
1260 __cpu_name[cpu] = "ICT Loongson-2"; in cpu_probe_legacy()
1262 set_isa(c, MIPS_CPU_ISA_III); in cpu_probe_legacy()
1263 c->fpu_msk31 |= FPU_CSR_CONDX; in cpu_probe_legacy()
1266 c->cputype = CPU_LOONGSON64; in cpu_probe_legacy()
1267 __cpu_name[cpu] = "ICT Loongson-3"; in cpu_probe_legacy()
1269 set_isa(c, MIPS_CPU_ISA_M64R1); in cpu_probe_legacy()
1270 c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM | in cpu_probe_legacy()
1275 c->cputype = CPU_LOONGSON64; in cpu_probe_legacy()
1276 __cpu_name[cpu] = "ICT Loongson-3"; in cpu_probe_legacy()
1278 set_isa(c, MIPS_CPU_ISA_M64R1); in cpu_probe_legacy()
1279 c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM | in cpu_probe_legacy()
1284 c->options = R4K_OPTS | in cpu_probe_legacy()
1287 c->tlbsize = 64; in cpu_probe_legacy()
1288 set_cpu_asid_mask(c, MIPS_ENTRYHI_ASID); in cpu_probe_legacy()
1289 c->writecombine = _CACHE_UNCACHED_ACCELERATED; in cpu_probe_legacy()
1292 decode_configs(c); in cpu_probe_legacy()
1294 c->cputype = CPU_LOONGSON32; in cpu_probe_legacy()
1296 switch (c->processor_id & PRID_REV_MASK) { in cpu_probe_legacy()
1298 __cpu_name[cpu] = "ICT Loongson-1"; in cpu_probe_legacy()
1306 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) in cpu_probe_mips() argument
1308 c->writecombine = _CACHE_UNCACHED_ACCELERATED; in cpu_probe_mips()
1309 switch (c->processor_id & PRID_IMP_MASK) { in cpu_probe_mips()
1311 c->writecombine = _CACHE_UNCACHED; in cpu_probe_mips()
1312 c->cputype = CPU_QEMU_GENERIC; in cpu_probe_mips()
1316 c->cputype = CPU_4KC; in cpu_probe_mips()
1317 c->writecombine = _CACHE_UNCACHED; in cpu_probe_mips()
1322 c->cputype = CPU_4KEC; in cpu_probe_mips()
1323 c->writecombine = _CACHE_UNCACHED; in cpu_probe_mips()
1328 c->cputype = CPU_4KSC; in cpu_probe_mips()
1329 c->writecombine = _CACHE_UNCACHED; in cpu_probe_mips()
1333 c->cputype = CPU_5KC; in cpu_probe_mips()
1334 c->writecombine = _CACHE_UNCACHED; in cpu_probe_mips()
1338 c->cputype = CPU_5KE; in cpu_probe_mips()
1339 c->writecombine = _CACHE_UNCACHED; in cpu_probe_mips()
1343 c->cputype = CPU_20KC; in cpu_probe_mips()
1344 c->writecombine = _CACHE_UNCACHED; in cpu_probe_mips()
1348 c->cputype = CPU_24K; in cpu_probe_mips()
1349 c->writecombine = _CACHE_UNCACHED; in cpu_probe_mips()
1353 c->cputype = CPU_24K; in cpu_probe_mips()
1354 c->writecombine = _CACHE_UNCACHED; in cpu_probe_mips()
1358 c->cputype = CPU_25KF; in cpu_probe_mips()
1359 c->writecombine = _CACHE_UNCACHED; in cpu_probe_mips()
1363 c->cputype = CPU_34K; in cpu_probe_mips()
1364 c->writecombine = _CACHE_UNCACHED; in cpu_probe_mips()
1366 cpu_set_mt_per_tc_perf(c); in cpu_probe_mips()
1369 c->cputype = CPU_74K; in cpu_probe_mips()
1370 c->writecombine = _CACHE_UNCACHED; in cpu_probe_mips()
1374 c->cputype = CPU_M14KC; in cpu_probe_mips()
1375 c->writecombine = _CACHE_UNCACHED; in cpu_probe_mips()
1379 c->cputype = CPU_M14KEC; in cpu_probe_mips()
1380 c->writecombine = _CACHE_UNCACHED; in cpu_probe_mips()
1384 c->cputype = CPU_1004K; in cpu_probe_mips()
1385 c->writecombine = _CACHE_UNCACHED; in cpu_probe_mips()
1387 cpu_set_mt_per_tc_perf(c); in cpu_probe_mips()
1390 c->cputype = CPU_1074K; in cpu_probe_mips()
1391 c->writecombine = _CACHE_UNCACHED; in cpu_probe_mips()
1395 c->cputype = CPU_INTERAPTIV; in cpu_probe_mips()
1397 cpu_set_mt_per_tc_perf(c); in cpu_probe_mips()
1400 c->cputype = CPU_INTERAPTIV; in cpu_probe_mips()
1402 cpu_set_mt_per_tc_perf(c); in cpu_probe_mips()
1405 c->cputype = CPU_PROAPTIV; in cpu_probe_mips()
1409 c->cputype = CPU_PROAPTIV; in cpu_probe_mips()
1413 c->cputype = CPU_P5600; in cpu_probe_mips()
1417 c->cputype = CPU_P6600; in cpu_probe_mips()
1421 c->cputype = CPU_I6400; in cpu_probe_mips()
1425 c->cputype = CPU_I6500; in cpu_probe_mips()
1429 c->cputype = CPU_M5150; in cpu_probe_mips()
1433 c->cputype = CPU_M6250; in cpu_probe_mips()
1438 decode_configs(c); in cpu_probe_mips()
1442 mm_config(c); in cpu_probe_mips()
1444 switch (__get_cpu_type(c->cputype)) { in cpu_probe_mips()
1447 set_isa(c, MIPS_CPU_ISA_M32R5); in cpu_probe_mips()
1450 c->options |= MIPS_CPU_SHARED_FTLB_ENTRIES; in cpu_probe_mips()
1453 c->options |= MIPS_CPU_SHARED_FTLB_RAM; in cpu_probe_mips()
1459 /* Recent MIPS cores use the implementation-dependent ExcCode 16 for in cpu_probe_mips()
1462 switch (__get_cpu_type(c->cputype)) { in cpu_probe_mips()
1468 c->options |= MIPS_CPU_FTLBPAREX; in cpu_probe_mips()
1473 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu) in cpu_probe_alchemy() argument
1475 decode_configs(c); in cpu_probe_alchemy()
1476 switch (c->processor_id & PRID_IMP_MASK) { in cpu_probe_alchemy()
1479 c->cputype = CPU_ALCHEMY; in cpu_probe_alchemy()
1480 switch ((c->processor_id >> 24) & 0xff) { in cpu_probe_alchemy()
1495 if ((c->processor_id & PRID_REV_MASK) == 2) in cpu_probe_alchemy()
1507 c->cputype = CPU_ALCHEMY; in cpu_probe_alchemy()
1513 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu) in cpu_probe_sibyte() argument
1515 decode_configs(c); in cpu_probe_sibyte()
1517 c->writecombine = _CACHE_UNCACHED_ACCELERATED; in cpu_probe_sibyte()
1518 switch (c->processor_id & PRID_IMP_MASK) { in cpu_probe_sibyte()
1520 c->cputype = CPU_SB1; in cpu_probe_sibyte()
1523 if ((c->processor_id & PRID_REV_MASK) < 0x02) in cpu_probe_sibyte()
1524 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR); in cpu_probe_sibyte()
1527 c->cputype = CPU_SB1A; in cpu_probe_sibyte()
1533 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu) in cpu_probe_sandcraft() argument
1535 decode_configs(c); in cpu_probe_sandcraft()
1536 switch (c->processor_id & PRID_IMP_MASK) { in cpu_probe_sandcraft()
1538 c->cputype = CPU_SR71000; in cpu_probe_sandcraft()
1540 c->scache.ways = 8; in cpu_probe_sandcraft()
1541 c->tlbsize = 64; in cpu_probe_sandcraft()
1546 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu) in cpu_probe_nxp() argument
1548 decode_configs(c); in cpu_probe_nxp()
1549 switch (c->processor_id & PRID_IMP_MASK) { in cpu_probe_nxp()
1551 c->cputype = CPU_PR4450; in cpu_probe_nxp()
1553 set_isa(c, MIPS_CPU_ISA_M32R1); in cpu_probe_nxp()
1558 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu) in cpu_probe_broadcom() argument
1560 decode_configs(c); in cpu_probe_broadcom()
1561 switch (c->processor_id & PRID_IMP_MASK) { in cpu_probe_broadcom()
1564 c->cputype = CPU_BMIPS32; in cpu_probe_broadcom()
1571 c->cputype = CPU_BMIPS3300; in cpu_probe_broadcom()
1577 int rev = c->processor_id & PRID_REV_MASK; in cpu_probe_broadcom()
1581 c->cputype = CPU_BMIPS4380; in cpu_probe_broadcom()
1584 c->options |= MIPS_CPU_RIXI; in cpu_probe_broadcom()
1587 c->cputype = CPU_BMIPS4350; in cpu_probe_broadcom()
1595 c->cputype = CPU_BMIPS5000; in cpu_probe_broadcom()
1596 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_BMIPS5200) in cpu_probe_broadcom()
1601 c->options |= MIPS_CPU_ULRI | MIPS_CPU_RIXI; in cpu_probe_broadcom()
1607 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu) in cpu_probe_cavium() argument
1609 decode_configs(c); in cpu_probe_cavium()
1611 c->options &= ~MIPS_CPU_4K_CACHE; in cpu_probe_cavium()
1612 switch (c->processor_id & PRID_IMP_MASK) { in cpu_probe_cavium()
1616 c->cputype = CPU_CAVIUM_OCTEON; in cpu_probe_cavium()
1623 c->cputype = CPU_CAVIUM_OCTEON_PLUS; in cpu_probe_cavium()
1633 c->cputype = CPU_CAVIUM_OCTEON2; in cpu_probe_cavium()
1641 c->cputype = CPU_CAVIUM_OCTEON3; in cpu_probe_cavium()
1647 c->cputype = CPU_UNKNOWN; in cpu_probe_cavium()
1655 static inline void decode_cpucfg(struct cpuinfo_mips *c) in decode_cpucfg() argument
1662 c->ases |= MIPS_ASE_LOONGSON_MMI; in decode_cpucfg()
1665 c->ases |= MIPS_ASE_LOONGSON_EXT; in decode_cpucfg()
1668 c->ases |= MIPS_ASE_LOONGSON_EXT2; in decode_cpucfg()
1671 c->options |= MIPS_CPU_LDPTE; in decode_cpucfg()
1672 c->guest.options |= MIPS_CPU_LDPTE; in decode_cpucfg()
1676 c->ases |= MIPS_ASE_LOONGSON_CAM; in decode_cpucfg()
1679 static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu) in cpu_probe_loongson() argument
1681 c->cputype = CPU_LOONGSON64; in cpu_probe_loongson()
1684 decode_configs(c); in cpu_probe_loongson()
1685 c->options |= MIPS_CPU_GSEXCEX; in cpu_probe_loongson()
1687 switch (c->processor_id & PRID_IMP_MASK) { in cpu_probe_loongson()
1688 case PRID_IMP_LOONGSON_64R: /* Loongson-64 Reduced */ in cpu_probe_loongson()
1689 switch (c->processor_id & PRID_REV_MASK) { in cpu_probe_loongson()
1694 __cpu_name[cpu] = "Loongson-2K"; in cpu_probe_loongson()
1696 set_isa(c, MIPS_CPU_ISA_M64R2); in cpu_probe_loongson()
1699 c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_EXT | in cpu_probe_loongson()
1702 case PRID_IMP_LOONGSON_64C: /* Loongson-3 Classic */ in cpu_probe_loongson()
1703 switch (c->processor_id & PRID_REV_MASK) { in cpu_probe_loongson()
1706 __cpu_name[cpu] = "ICT Loongson-3"; in cpu_probe_loongson()
1708 set_isa(c, MIPS_CPU_ISA_M64R2); in cpu_probe_loongson()
1712 __cpu_name[cpu] = "ICT Loongson-3"; in cpu_probe_loongson()
1714 set_isa(c, MIPS_CPU_ISA_M64R2); in cpu_probe_loongson()
1718 * Loongson-3 Classic did not implement MIPS standard TLBINV in cpu_probe_loongson()
1722 * Also some early Loongson-3A2000 had wrong TLB type in Config in cpu_probe_loongson()
1725 c->options |= MIPS_CPU_FTLB | MIPS_CPU_TLBINV | MIPS_CPU_LDPTE; in cpu_probe_loongson()
1726 c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM | in cpu_probe_loongson()
1728 c->ases &= ~MIPS_ASE_VZ; /* VZ of Loongson-3A2000/3000 is incomplete */ in cpu_probe_loongson()
1733 __cpu_name[cpu] = "ICT Loongson-3"; in cpu_probe_loongson()
1735 set_isa(c, MIPS_CPU_ISA_M64R2); in cpu_probe_loongson()
1736 decode_cpucfg(c); in cpu_probe_loongson()
1746 static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu) { } in cpu_probe_loongson() argument
1749 static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu) in cpu_probe_ingenic() argument
1751 decode_configs(c); in cpu_probe_ingenic()
1757 decode_config3(c); in cpu_probe_ingenic()
1760 c->options &= ~MIPS_CPU_COUNTER; in cpu_probe_ingenic()
1764 c->icache.flags |= MIPS_CACHE_VTAG; in cpu_probe_ingenic()
1766 switch (c->processor_id & PRID_IMP_MASK) { in cpu_probe_ingenic()
1779 switch (c->processor_id & PRID_COMP_MASK) { in cpu_probe_ingenic()
1787 c->isa_level &= ~MIPS_CPU_ISA_M32R2; in cpu_probe_ingenic()
1790 if (c->processor_id == 0x2ed0024f) in cpu_probe_ingenic()
1791 c->options |= MIPS_CPU_FPU; in cpu_probe_ingenic()
1800 * (line 21 in the tlb-funcs.S) when starting the init process. in cpu_probe_ingenic()
1816 /* Ingenic uses the WA bit to achieve write-combine memory writes */ in cpu_probe_ingenic()
1817 c->writecombine = _CACHE_CACHABLE_WA; in cpu_probe_ingenic()
1818 c->cputype = CPU_XBURST; in cpu_probe_ingenic()
1824 c->cputype = CPU_XBURST; in cpu_probe_ingenic()
1846 struct cpuinfo_mips *c = ¤t_cpu_data; in cpu_probe() local
1855 c->processor_id = PRID_IMP_UNKNOWN; in cpu_probe()
1856 c->fpu_id = FPIR_IMP_NONE; in cpu_probe()
1857 c->cputype = CPU_UNKNOWN; in cpu_probe()
1858 c->writecombine = _CACHE_UNCACHED; in cpu_probe()
1860 c->fpu_csr31 = FPU_CSR_RN; in cpu_probe()
1861 c->fpu_msk31 = FPU_CSR_RSVD | FPU_CSR_ABS2008 | FPU_CSR_NAN2008; in cpu_probe()
1863 c->processor_id = read_c0_prid(); in cpu_probe()
1864 switch (c->processor_id & PRID_COMP_MASK) { in cpu_probe()
1866 cpu_probe_legacy(c, cpu); in cpu_probe()
1869 cpu_probe_mips(c, cpu); in cpu_probe()
1873 cpu_probe_alchemy(c, cpu); in cpu_probe()
1876 cpu_probe_sibyte(c, cpu); in cpu_probe()
1879 cpu_probe_broadcom(c, cpu); in cpu_probe()
1882 cpu_probe_sandcraft(c, cpu); in cpu_probe()
1885 cpu_probe_nxp(c, cpu); in cpu_probe()
1888 cpu_probe_cavium(c, cpu); in cpu_probe()
1891 cpu_probe_loongson(c, cpu); in cpu_probe()
1897 cpu_probe_ingenic(c, cpu); in cpu_probe()
1902 BUG_ON(c->cputype == CPU_UNKNOWN); in cpu_probe()
1909 BUG_ON(current_cpu_type() != c->cputype); in cpu_probe()
1917 c->options |= MIPS_CPU_RIXIEX; in cpu_probe()
1921 c->options &= ~MIPS_CPU_FPU; in cpu_probe()
1924 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P); in cpu_probe()
1927 c->options &= ~MIPS_CPU_HTW; in cpu_probe()
1932 if (c->options & MIPS_CPU_FPU) in cpu_probe()
1933 cpu_set_fpu_opts(c); in cpu_probe()
1935 cpu_set_nofpu_opts(c); in cpu_probe()
1938 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1; in cpu_probe()
1940 c->options |= MIPS_CPU_PCI; in cpu_probe()
1943 c->srsets = 1; in cpu_probe()
1949 c->msa_id = cpu_get_msa_id(); in cpu_probe()
1950 WARN(c->msa_id & MSA_IR_WRPF, in cpu_probe()
1989 cpu_probe_vz(c); in cpu_probe()
1991 cpu_probe_vmbits(c); in cpu_probe()
1994 * no-op otherwise. in cpu_probe()
1998 loongson3_cpucfg_synthesize_data(c); in cpu_probe()
2002 __ua_limit = ~((1ull << cpu_vmbits) - 1); in cpu_probe()
2010 struct cpuinfo_mips *c = ¤t_cpu_data; in cpu_report() local
2013 smp_processor_id(), c->processor_id, cpu_name_string()); in cpu_report()
2014 if (c->options & MIPS_CPU_FPU) in cpu_report()
2015 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id); in cpu_report()
2017 pr_info("MSA revision is: %08x\n", c->msa_id); in cpu_report()
2026 cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_CLUSTER; in cpu_set_cluster()
2027 cpuinfo->globalnumber |= cluster << MIPS_GLOBALNUMBER_CLUSTER_SHF; in cpu_set_cluster()
2035 cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_CORE; in cpu_set_core()
2036 cpuinfo->globalnumber |= core << MIPS_GLOBALNUMBER_CORE_SHF; in cpu_set_core()
2048 cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_VP; in cpu_set_vpe_id()
2049 cpuinfo->globalnumber |= vpe << MIPS_GLOBALNUMBER_VP_SHF; in cpu_set_vpe_id()
2057 struct cpuinfo_mips *c = ¤t_cpu_data; in cpu_disable_mmid() local
2065 set_cpu_asid_mask(c, asid_mask); in cpu_disable_mmid()
2073 c->options &= ~MIPS_CPU_MMID; in cpu_disable_mmid()