Lines Matching refs:t1
148 1: PTR_L t1, VPEBOOTCFG_PC(v1)
151 jr t1
207 PTR_LA t1, 1f
208 jr.hb t1
238 sll t1, ta1, VPECONF0_XTC_SHIFT
239 or t0, t0, t1
275 li t1, COREBOOTCFG_SIZE
276 mul t0, t0, t1
277 PTR_LA t1, mips_cps_core_bootcfg
278 PTR_L t1, 0(t1)
279 PTR_ADDU v0, t0, t1
297 mfc0 t1, CP0_MVPCONF0
298 srl t1, t1, MVPCONF0_PVPE_SHIFT
299 andi t1, t1, MVPCONF0_PVPE >> MVPCONF0_PVPE_SHIFT
300 addiu t1, t1, 1
303 clz t1, t1
305 subu t1, t2, t1
307 sll t1, t2, t1
308 addiu t1, t1, -1
312 and t9, t9, t1
316 li t1, VPEBOOTCFG_SIZE
317 mul v1, t9, t1
334 PTR_LA t1, mips_gcr_base
335 PTR_L t1, 0(t1)
336 PTR_L t1, GCR_CPC_BASE_OFS(t1)
338 and t1, t1, t2
340 PTR_ADD t1, t1, t2
343 PTR_S ta2, CPC_CL_VC_RUN_OFS(t1)
347 PTR_S ta2, CPC_CL_VC_STOP_OFS(t1)
362 PTR_LA t1, 1f
363 jr.hb t1
365 1: mfc0 t1, CP0_MVPCONTROL
366 ori t1, t1, MVPCONTROL_VPC
367 mtc0 t1, CP0_MVPCONTROL
402 lw t1, VPEBOOTCFG_PC(t0)
403 mttc0 t1, CP0_TCRESTART
406 lw t1, VPEBOOTCFG_SP(t0)
407 mttgpr t1, sp
410 lw t1, VPEBOOTCFG_GP(t0)
411 mttgpr t1, gp
438 li t1, ~TCSTATUS_IXMT
439 and t0, t0, t1
458 mfc0 t1, CP0_MVPCONTROL
459 xori t1, t1, MVPCONTROL_VPC
460 mtc0 t1, CP0_MVPCONTROL
509 li t1, 2
510 sllv t0, t1, t0
513 _EXT t1, v0, MIPS_CONF1_IS_SHF, MIPS_CONF1_IS_SZ
514 xori t2, t1, 0x7
517 addiu t1, t1, 1
518 sllv t1, t3, t1
522 mul t1, t1, t0
523 mul t1, t1, t2
526 PTR_ADD a1, a0, t1
536 li t1, 2
537 sllv t0, t1, t0
540 _EXT t1, v0, MIPS_CONF1_DS_SHF, MIPS_CONF1_DS_SZ
541 xori t2, t1, 0x7
544 addiu t1, t1, 1
545 sllv t1, t3, t1
549 mul t1, t1, t0
550 mul t1, t1, t2
553 PTR_ADDU a1, a0, t1
584 psstate t1
592 psstate t1