Lines Matching +full:non +full:- +full:core
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
10 #include <asm/asm-offsets.h>
17 #include <asm/smp-cps.h>
55 * Set dest to non-zero if the core supports the MT ASE, else zero. If
70 * Set dest to non-zero if the core supports MIPSr6 multithreading
135 /* Skip core-level init if we started up coherent */
139 /* Perform any further required core-level initialisation */
144 * Boot any other VPEs within this core that should be online, and
199 /* Check that the core implements the MT ASE */
220 /* Retrieve the number of VPEs within the core */
230 /* Loop through each VPE within this core */
240 /* Set exclusive TC, non-active, master */
246 /* Set TC non-active, non-allocatable */
271 * mips_cps_get_bootcfg() - retrieve boot configuration pointers
294 /* Calculate this VPEs ID. If the core doesn't support MT use 0 */
300 * Assume non-contiguous numbering. Perhaps some day we'll need
309 /* Find the number of VPEs present in the core */
321 addiu t1, t1, -1
365 /* If the core doesn't support MT then return */
432 * CONFIG3 must exist to be running MT startup - just read it.
519 /* Detect I-cache line size */
525 /* Detect I-cache size */
532 1: /* At this point t1 == I-cache sets per way */
546 /* Detect D-cache line size */
552 /* Detect D-cache size */
559 1: /* At this point t1 == D-cache sets per way */